SHF: Small: Test Chip Design for Maximal Yield Learning

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

Integrated circuits are pervasive, found in everything from mobile phones and televisions, to cars and airplanes. In order to continue to produce new and more-capable electronics, it is necessary to develop techniques for creating example electronic systems that provides critical information about how to improve the design and fabrication of integrated circuits. This NSF-funded project is focused on developing a design approach for creating integrated circuits that closely resemble electronics actually used in phones, televisions, etc. but also have the property that they can be easily diagnosed when they fail to work properly due to non-idealities in design and/or manufacturing. The knowledge learned from diagnosis will then allow the design and manufacturing to be improved in order to reduce/prevent integrated circuits for actual products (phones, cars, etc.) from failing. Under the support of the NSF program, an integrated circuit design methodology based on logic-function regularity will be developed. The planned methodology produces a test circuit that reflects various physical aspects of actual integrated circuits used in everyday products while guaranteeing optimal test and diagnosis characteristics. The methodology will allow both designers and manufacturers of integrated circuits to produce new, more capable integrated electronics for future products. Example circuits will be design and manufactured in collaboration with industrial partners to demonstrate the capabilities of the methodology.