ITR (ASE + NHS) - (sim + dmc): Infrastructure Creation for Future Generation Test, Diagnosis and Yield Learning

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

ABSTRACT 0427382 Blanton, Ronald CMU Significant yield degradation is expected from design-fabrication interactions that are also known as systematic defects. Because our ability to see these defects is quickly diminishing, test will become the main source of insight into these failures. In other words, in addition to its normal sorting function, test will be the essential feedback loop for understanding the failure mechanisms inherent in complex fabrication processes. Specifically, test will be the key enabler for characterizing defects, unacceptable parametric variations, and design-process interactions essential for yielding reliable, working products in both a timely and cost-effective manner. To meet this challenge, new efficient approaches to test, testability analysis, design-for-test, built-in self test, and diagnosis must be developed that can cope with the variety of failure types expected in futuregeneration products. Research in this area is restricted however since current test tools (i.e. fault simulators and test generators) are limited in the variety of failures that they can directly analyze. To remedy this situation, a fault tuple based infrastructure will be developed and disseminated that will enable researchers in the field of design, test and manufacturing to develop new and efficient approaches to test. The fault tuple mechanism is a general and effective methodology for analyzing failures in digital integrated circuits. Its key characteristic is its ability to precisely model the effects of any arbitrary failure mechanism on the logical behavior of a digital circuit. The proposed infrastructure includes the development, implementation and dissemination of (i) a fault tuple simulator, (ii) a fault tuple test generator, (iii) a set of fault generators (i.e. software modules that extract fault tuple models of a given defect type from the chip design), and (iv) accompanying documentation that details capabilities and limitations of the test tools. We believe creation of the proposed infrastructure will not only allow researchers to effectively evaluate their approaches to test but enable them to develop totally new, innovative test methodologies that are impossible within the current infrastructure.