← Leaderboards
Madhavan Swaminathan
Rochester Institute Of Tech
$3,350,276
Attributed
$5,948,083
Total exposure
13
Grants
6
Lead (contact PI)
Attributed= this PI's even-split share of every grant they're on (the fair, additive number). Exposure = full size of all those grants.
Funding over time
peak $2.2M · FY2005–24$2.5M$1.9M$1.3M$625K$0
'05
'06
'07
'08
'09
'10
'11
'12
'13
'14
'15
'16
'17
'18
'19
'20
'21
'22
'23
'24
Funding mix
By agency
NSF$5,948,083 · 13
By mechanism
—$5,948,083 · 13
Top collaborators
- Elyse Rosenbaum3 shared
- Paul D Franzon3 shared
- Suresh K Sitaraman2 shared
- Arijit Raychowdhury1 shared
- Jayanti Venkataraman1 shared
- Mark J Rodwell1 shared
- Matthieu Bloch1 shared
- P. R Mukund1 shared
Grant awards (13)
Fuse2 Topic 2: Heterogeneously Integrated Arrays for Massively Scalable sub-THz Communications and Sensing$1,026,122
· FY2024 · ENG
IUCRC Phase II Georgia Institute of Technology: Center for Advanced Electronics through Machine Learning [CAEML]$474,475
· FY2023 · CSE · contact PI
RINGS: Just-in-Time Security: Adaptive Physical-Layer Security for NextG Low-Latency mmWave Wireless Networks$1,007,428
· FY2022 · CSE
IUCRC Phase II North Carolina State University: Center for Advanced Electronics through Machine Learning [CAEML]$500,000
· FY2022 · CSE
IUCRC Phase II University of Illinois Urbana Champaign: Center for Advanced Electronics through Machine Learning (CAEML)$500,000
· FY2022 · CSE
IUCRC Phase II Georgia Institute of Technology: Center for Advanced Electronics through Machine Learning [CAEML]$200,000
· FY2022 · CSE · contact PI
I/UCRC: Center for Advanced Electronics through Machine Learning (CAEML)$750,000
· FY2016 · CSE · contact PI
Collaborative Research: Planning Grant: I/UCRC for Advanced Electronics through Machine Learning$11,500
· FY2015 · ENG · contact PI
Design and Modeling Framework for Managing Variability in Silicon Interposers for 3D Integration$387,415
· FY2011 · ENG · contact PI
Offchip Interconnect Signaling Scheme with Near Zero Simultaneous Switching Noise$360,001
· FY2010 · ENG · contact PI
DEVELOPMENT OF COMPLIANT FREE-STANDING STRUCTURES FOR SUB 32-nm MULTI-CORE ICs$350,000
· FY2009 · ENG
SGER: Innovative Off-Chip Interconnects for 45-nm and sub-45-nm Node ICs$74,999
· FY2005 · ENG
Chip-Package Co-Design Methodology for Integrated RF Microsystems$306,143
· FY2001 · ENG