ULTRA-LOW POWER CMOS-COMPATIBLE INTEGRATED PHOTONIC PLATFORM FOR TERABIT-SCALE COMMUNICATIONSOUR PROPOSED EFFORT EXPLOITS RECENT BREAKTHROUGH 3D MONOLITHIC INTEGRATION OF PHOTONIC STRUCTURES PARTICULARLY HIGH-SPEED GRAPHENESILICON DEVICES ON CMOS ELECTRONICS TO CREATE A CMOS-COMPATIBLE PLATFORM FOR ULTRA-LOW POWER TERABIT-SCALE OPTICAL COMMUNICATIONS. THE PROPOSED FULLY CMOS-COMPATIBLE 3D PLATFORM ENABLES PHOTONIC TRANSMISSION OF USER-PROGRAMMABLE VARIABLE DATA RATES RANGING FROM 10'S OF MHZ TO 100'S OF GHZ WITHIN THE CRITICAL ULTRA LOW POWER (1-10W) ENVELOPE ESSENTIAL FOR OPTICAL SPACE COMMUNICATIONS APPLICATIONS. THE ARCHITECTURE ENABLES IMPLEMENTATION OF GRAPHENE-SILICON STRUCTURES WITH UNPRECEDENTED DATA MODULATION SPEEDS OFFERING FOR THE FIRST TIME A TRULY SCALABLE ULTRA-LOW ENERGY TERABIT-SCALE OPTICAL SPACE COMMUNICATIONS INFRASTRUCTURE. CURRENT STATE-OF-THE-ART FREE SPACE LASER LINKS AT TELECOMMUNICATIONS WAVELENGTHS ARE LIMITED IN BANDWIDTH TO<1GBPS MAINLY DUE TO THE HIGH ENERGY CONSUMPTION ASSOCIATED WITH SCALING TO HIGHER SPEEDS AND BANDWIDTH DENSITIES. IN THIS EFFORT WE PROPOSE A COMPLETELY CMOS COMPATIBLE INTEGRATED PHOTONIC COMMUNICATIONS PLATFORM THAT UNIQUELY ENABLES ULTRA-LOW POWER AND EXTREMELY HIGH-SPEED DATA DELIVERY. THE COMMUNICATION ARCHITECTURE INCORPORATES RECENT BREAKTHROUGHS BY OUR TEAM ON NOVEL SILICON-GRAPHENE PHOTONIC MODULATORS CAPABLE OF 100'S OF GBPS DATA RATES. THE PROPOSED PLATFORM IS BASED ON 3D MONOLITHIC INTEGRATION OF PHOTONIC STRUCTURES ON CMOS ELECTRONICS WHICH LEVERAGES THE FULL-SCALE CAPABILITY OF THE CMOS MANUFACTURING INFRASTRUCTURE WHILE ENABLING INTEGRATION WITH HIGH PERFORMANCE PHOTONIC DEVICES. THE HIGH SPEED MODULATORS ARE THUS FULLY COMPATIBLE WITH CMOS ELECTRONICS. THIS UNIQUE PLATFORM ADVANTAGEOUSLY BREAKS THE HIGH POWER CONSUMPTION/HIGH BANDWIDTH TRADE-OFF OF PRIOR GENERATION SILICON PHOTONICS. THE PROPOSED ULTRA-LOW POWER CMOS COMPATIBLE PLATFORM WILL ENABLE TERABIT-SCALE COMMUNICATIONS IN SPACE AND UNLOCK THE POTENTIAL OF FREE SPACE LASER LINKS. BASED ON THE PROPOSED PLATFORM WE PLAN TO DEMONSTRATE AN INTEGRATED PHOTONIC LINK TRANSCEIVER CAPABLE OF VARIABLE USERPROGRAMMABLE BANDWIDTHS FROM 10'S OF MHZ TO 100'S GHZ THAT INTERFACES SEAMLESSLY WITH CUTTING EDGE ERROR CORRECTION SCHEMES AND IS SCALABLE TO TERABIT/SEC COMMUNICATIONS. THE EFFORT WILL FURTHER LEVERAGE OUR LEADING 3D MONOLITHIC INTEGRATION CAPABILITIES OF PHOTONIC STRUCTURES TO DEMONSTRATE A CMOS COMPATIBLE PLATFORM CAPABLE OF INTEGRATING THE COMPLETE COMMUNICATION ON-CHIP SYSTEM INCLUDING HIGH PERFORMANCE MODULATORS ROUTERS WAVEGUIDES AND DETECTORS. THE FUTURE DEVELOPMENT OF THE PLATFORM NATURALLY LEADS TO THE DEMONSTRATION OF FULL TRANSCEIVERS AND RECEIVERS MONOLITHICALLY INTEGRATED WITH CMOS ELECTRONICS ON A CHIP WITH INTEGRATED ERROR CORRECTION.