HCC: Medium: Software-Hardware Codesign for Real-Time Ray Tracing

University Of Utah, Salt Lake City UT

Investigators

Abstract

Computer graphics uses a range of techniques to create and manipulate both 2D and 3D images. Graphics users have to balance quality and timing when creating or adjusting images. This project addresses this tradeoff with both hardware and software techniques to accelerate ray tracing - a technique for computer graphic rendering that generates tremendously realistic images by simulating the physics of how light interacts with physical objects. While ray tracing is the gold standard for rendering realistic images where the time taken to do the rendering is less important than the quality of the final result, interactive rendering (games, data visualization, virtual reality, etc.) rely on a different technique, rasterization. Rasterization is well-supported by commercial graphics processing units (GPUs), but does not accurately represent realistic optical effects such as shadows, reflections, refraction, global illumination, glossy/specular materials. Improving the performance of ray tracing can bring its power to generate highly realistic images to bear on a whole new range of important problems that must run at interactive rates. Despite the clear advantages of ray tracing, virtually all GPUs are designed primarily to accelerate rasterization. The ray tracing cores included in some GPUs automate the ray traversal and intersection routines, but data movement remains a fundamental problem to improving performance. This project targets the data movement problem with ray tracing by compressing ray data and reordering the related computations. It investigates methods for coalescing rays that access the same memory block so that they may be processed together, thereby reducing repeated and unstructured memory accesses. This involves keeping track of the rays in flight and interrupting ray traversal to prevent premature memory access before they can be coalesced and handled efficiently. One specific technique being explored is reduced precision data representations with specialized hardware support and optimized storage of triangles within treelets. This project is also exploring alternative scene data representations other than bounding volume hierarchies (BVHs). While BVHs are known to provide good performance with traditional ray tracing on existing hardware, custom hardware could favor different representations. Therefore, the project explores both software/algorithmic modifications to ray traversal and special-purpose hardware designs targeting the modified traversal and data movement patterns. A modular and parallel cycle-level hardware simulator is developed to test the novel hardware designs, identify the bottlenecks, and iteratively improve them. This hardware simulator will also be publicly released and maintained as a part of this project. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.