SaTC: CORE: Small: NSF-DST: ENCASE: Co-Design of Electromagnetics, Nanomaterials, Circuits and Architectures for Generic Protection against Side-Channel Emanation

University Of Florida, Gainesville FL

Investigators

Abstract

With the proliferation of high-tech gadgets such as smartphones, tablets, wearables, and smart-home devices, the amount of data that needs to be made secure is increasing. Malicious attackers target even encrypted devices to steal confidential information using advanced techniques. Side-channel attacks, which exploit various sources of leakage such as power consumption, timing data, and electromagnetic (EM) emissions from a computing device during data handling processes, are commonly utilized to breach the security of integrated circuits (ICs). Due to their cost-effectiveness and potentially non-intrusive methods, these attacks pose a significant threat to the confidentiality of personal, commercial, and military data. This project leverages the synergetic collaborative effort between the USA and Indian research teams to provide security against power and EM side-channel attacks at different abstraction levels, including EM analysis, circuit/logic/layout design, and architectural/system-level choices. The project develops secure libraries and tools that can be used by circuit design engineers and a scientific methodology to evaluate EM and power side-channels in custom ICs. The outcome of this project makes a positive impact on the electronics industry through security-aware design, pre-Silicon side-channel vulnerability analysis, and quantifying security using commercial design tools. This project also provides integrative, multidisciplinary training to graduate and undergraduate students on a multitude of technical areas such as security-aware circuit, layout and package design, development of custom tool flows, and characterization/quantification of security on hardware devices. This project also fosters increased collaboration between USA and Indian researchers, potentially setting the foundations for long-term engagement and scientific partnerships. The project team's technical approach entails a massive co-design of electromagnetics, materials, circuits and architecture for secure IC design. To this end, this USA team conducts the research on modeling of the EM and power side channels for various real-world devices, along with the design and analysis of on-chip side-channel countermeasures. The Indian research team leads the pre-silicon side-channel security analysis for EM and power, as well as standard cell library design for security enhancement. The design of the side-channel secure standard-cell library utilizes a novel split-pole based CMOS design methodology that creates complementary dipoles to cancel EM emanation at the gate level. This effort is complemented with side-channel aware on-chip global routes utilizing dipole, quadrupole, and higher order EM emission characteristics, which helps in reducing EM side-channel leakage resulting from long on-chip metal lines. Designing encryption cores with the side-channel secure standard cell library is further benefitted from a configurable, design-tool-friendly version of a custom current-domain signature attenuation circuit. The research team is also exploring design-tool-aware and timing-aware clock path optimization techniques to reduce the EM and power side-channels. Additionally, material properties of metal layers in CMOS ICs are being analyzed to provide potentially better side-channel resistance for both IC-level and three-dimensional (3D) integrated package-level implementations. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.