SHF: Small: Machine Learning-based Combinatorial Optimization for Electronic Design Automation and Beyond

Brown University, Providence RI

Investigators

Abstract

Electronic Design Automation (EDA) tools enable the design, analysis, and manufacturing of chips at an unprecedented scale. However, these tools are limited by their reliance on heuristic-based optimization and expert knowledge, which can slow down the chip design process, sometimes taking months or even years. To address this inefficiency, this project introduces an initiative to enhance design productivity by integrating Machine Learning (ML) techniques into EDA optimization algorithms. This integration aims to improve both the performance and speed of these algorithms, potentially revolutionizing the way chip designs are completed. The broader impacts of this project include extensive educational outreach and industry transfer efforts in line with the CHIPS and Science Act, aiming to enhance semiconductor research and workforce training in an Estab­lished Program to Stim­u­late Com­pet­i­tive Research (EPSCoR) state. The proposed ML-EDA co-optimization framework seeks to standardize the application of ML in core EDA combinatorial optimizations across various scenarios. By developing numerical embeddings of chip design instances at every stage of the EDA process, these embeddings are utilized as input features for ML-based optimizations. This setup allows for optimizations that are tailored to specific design instances, leveraging three innovative ML engines: deep metric learning for optimal hyperparameter selection, reinforcement learning for sequential decision-making in EDA tools, and a back-propagation approach that restructures combinatorial EDA problems into graph-based computing models for faster, more effective solutions. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.