FET: Medium: Scalable and Ultra-Low-Power Neural Accelerators based on 2D Ferroelectric Semiconductors (SAFES)

Purdue University, West Lafayette IN

Investigators

Abstract

The remarkable success of artificial intelligence (AI) in tasks involving recognition, natural language processing, sensory processing and many others has motivated the development of custom hardware accelerators for neural computing. However, the existing neural hardware solutions exhibit an alarmingly low energy efficiency, due to which their deployment in resource-constrained edge devices is highly challenging. This research aims at addressing the hardware needs for future AI platforms by developing design solutions that push the boundaries of the state-of-the-art to deliver significant enhancements in the energy efficiency and scalability. This will be achieved by utilizing the unique properties of ferroelectric semiconductors (FeS) amenable to neural computing and designing ultra-low power circuits and architectures based on them. The proposed energy efficient design techniques will enable the development of AI hardware capable of processing neural workloads on the edge and therefore, will make a positive impact on critical applications such as computer aided diagnosis, robotics, speech/face recognition, data classification etc. This will directly benefit several areas such as healthcare, defense, and security, among others. Further, the project will utilize the research outcomes to enhance the graduate curriculum and will promote the participation of undergraduate and minority students in the proposed research to introduce them to the field of AI based on emerging technologies. A pressing need for next-generation computing is to meet the humungous data processing needs of future AI workloads, for which computing-in-memory (CiM) shows an immense promise. However, existing CiM techniques are plagued by huge energy/area overheads of analog-to-digital converters (ADCs), limited scalability of memory technologies and device-circuit non-idealities. This project aims to overcome these challenges at various levels of design abstraction to achieve a systemic improvement in area- and energy-efficiencies and computational robustness. The material-level exploration will include experimental and first-principles studies of Indium Selenide (In2Se3) - a unique 2D material with ferroelectric and semiconducting properties, which makes it suitable for both compute and memory functionalities. At the device level, fabrication of FeS-based devices coupled with their phase-field modeling will be carried out to design compute-amenable non-volatile memory devices. At the circuit level, FeS-based multi-level synaptic crossbar macros, (near)-ADC-less designs and fault-tolerant CiM will be investigated to achieve compact, robust and energy efficient solutions. At the architecture level, hierarchical deep neural network (DNN) architectures optimized for CiM and featuring hardware-training co-design will be developed for ultra-low power operation along with high inference accuracy. To facilitate such a cross-layer design, a devices-to-systems simulation framework for FeS-based DNNs will be built. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.