ERI: Hardware-Constraint-Aware Design and Optimization of Memristor-Crossbar-Array (MCA) based Neural Network Accelerators

Southern Illinois University At Carbondale, Carbondale IL

Investigators

Abstract

In the rapidly evolving landscape of computing, a transformative technology known as memristor-crossbar array (MCA) chips is poised to revolutionize the way we interact with technology. MCA chips consist of memristor devices organized in a grid-like structure, representing a promising foundational element for neuromorphic computing. MCA chips are expected to integrate into various aspects of our daily lives, enhancing efficiency and connectivity on a global scale. By offering high energy efficiency and brain-inspired information processing capabilities, MCA chips have the potential to reshape industries such as healthcare, robotics, and autonomous systems. Despite the transformative potential, the design process for MCA chips faces a significant challenge: a disconnect between software design tools and the physical limitations of the hardware. This disconnect often leads to performance degradation or even functional failure, resulting in costly setbacks and delays in development. As a result, extensive on-chip training procedures are typically required, further increasing the development cost, and prolonging the time to market. Thus, bridging the gap between software design tools and hardware constraints is crucial for realizing the full potential of MCA technology and expediting its integration into various applications. The outcomes of this research will be used in many industry sectors that rely on neuromorphic computing, thus producing an enormous value in the industry, economy, and society. This research will address the critical challenges inherent in the design process of MCA chips. The first research involves modeling and integrating the physical constraints of memristor devices and analog circuits into software design tools for constraint-aware training and batch normalization (BN) fusion strategy. This research effort will create accurate and efficient training processes while reducing the reliance on costly on-chip training methods. Removing expensive on-chip training is essential for advancing the large-scale adoption and commercialization of memristor-based technologies in various applications, enabling cost-effective, efficient, and scalable computing solutions. In addition, we will develop an efficient hardware architecture that seamlessly aligns with software-trained models, facilitating a smooth transition from the software design domain to hardware implementation. Furthermore, we will develop transformation tools to enable rapid prototyping and deployment of software-trained models on MCA chips. Through these efforts, we anticipate achieving significant advancements in MCA chip design, resulting in enhanced performance, scalability, and cost-effectiveness. This research will fundamentally improve the prevailing design approach and paradigm for MCA-based chips, automate the entire design cycle and enable software-hardware co-design of MCA chips. Therefore, this research will contribute to the broader goal of advancing artificial intelligence and cognitive computing through the development of efficient and innovative edge computing technologies. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.