CAREER: Next Generation of High-Level Synthesis for Agile Architectural Design (ArchHLS)

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

In the landscape of computing, the demand for innovative hardware architectures is ever-growing, driving advancements in computer architecture. However, the conventional Register Transfer Level (RTL) design approach is time-consuming and labor-intensive. This project aims to facilitate the broader adoption of High-Level Synthesis (HLS) tools to significantly reduce design time, particularly for general architectural design. HLS tools enable higher-level programming and automatic synthesis, yet their application in comprehensive computer architecture studies remains limited. The significance of this project lies in promoting agile hardware development by fundamentally innovating HLS tools, overcoming the productivity challenges at the register transfer level, and unlocking the potential for more widespread application of HLS in diverse computing domains. The developed tool chain will be publicly available and exposed to more users by organizing tutorials, workshops, and demo events. The research will be integrated into education programs with activities on research training for undergraduate and master students, including online students, recruitment and retention of students from underrepresented groups, curriculum development, and innovative international design competitions co-hosted with industry. This project aims to revolutionize High-Level Synthesis (HLS) tools by introducing a next-generation tool, ArchHLS, addressing two major research challenges. First, HLS tools are superior in synthesizing a specific algorithm into hardware but have limited capability for general domain-specific architecture designs. Second, it is challenging to design general architectures with compatible compilers and to automatically improve the underlying architecture for evolving workloads. To address these challenges, ArchHLS facilitates agile hardware development by making three key innovations. First, ArchHLS decouples architectural design and workload mapping, allowing flexible architecture extraction and customized control flow. Second, ArchHLS automates architecture evolution to adapt to fast-changing algorithms via automated workload compilation, mapping, and computation pattern matching. Third, ArchHLS enables comprehensive and accurate performance profiling for designs to provide feedback for architecture evolution. Beyond advancing Electronic Design Automation (EDA) tooling, this research has broader societal implications, aligning with the grand vision of sustainability for computing and computing for sustainability, such as climate modeling and scientific computing. The public availability of the toolchain fosters research dissemination, educational integration, and inclusivity efforts, aiming to benefit diverse communities and promote efficient algorithm/architecture co-design. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.