CAREER: Building Scalable and Reliable Composable Computer Architectures

University Of California - Merced, Merced CA

Investigators

Abstract

In the post-Moore era, computing platforms have become more diverse and heterogeneous. With the evolution of packaging and interconnect technology, multiple computing and memory components are integrated into a single processor package. The high-bandwidth and coherent interconnects enable multiple accelerators and memory components on a platform together achieve server scale computing power. Though this new paradigm of computing platforms enables more optimal processor designs for domain-specific computing, the scalability is unclear. The fast interconnects between intra- and inter-chip components do not necessarily lead to linear speedup unless the communications are carefully handled. This project aims to keep up with performance projection of Moore’s law in post-Moore era with scalable architecture-level solutions. As graphics processing units (GPUs) are increasingly important for accelerating big data workloads, this project will focus on architecting highly scalable and reliable GPU platforms that can achieve almost linear speedup with the scaling of GPU chiplet modules and memory devices. The presented research tools and virtual memory systems will advance the state-of-the-art architectures with coherent and scalable communications among the intra- and inter-GPU chiplet components. The presented architecture design will be able to accelerate emerging big-data workloads without needing to access expensive cloud or data center supercomputers. The research findings will be incorporated into new and existing undergraduate and graduate courses as well as K-12 outreach programs. This project aims to address the following research questions: 1) How to manage all the integrated computing and memory components to communicate efficiently? Can the conventional virtual memory system handle large volumes of address translations? 2) How to achieve scalable and sustainable performance over multi-level non-uniform memory access (NUMA) architectures? Can consistent data access latency be enforced? This project answers these questions through two technical thrusts. The first thrust will design research tools that enable design explorations of scalable and heterogeneous platforms. Then, efficient virtual memory systems and page mapping algorithms will be architected. Unlike existing solutions, the methods presented in this project will exploit the unique GPU execution model while enabling coherent communication among intra- and inter-GPU packages. The second thrust will explore methods to enforce sustainable performance on the target multi-GPU systems having disaggregated memories. These new platforms have emerging challenges of deeper NUMA levels than conventional systems because individual computing and memory components can be integrated through multiple levels of extensible switches. This thrust will design efficient memory management and prefetch algorithms, which together enforce data to be ready within 1-2 NUMA distances. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.