FMitF: Track I: A Holistic Approach Towards Online Monitoring of Integrated Circuits and Systems

William Marsh Rice University, Houston TX

Investigators

Abstract

The ever-increasing complexity of chip design and system integration, the reliance on third-party hardware components, and the untrustworthy global semiconductor supply chains open up the possibility for the introduction of errors. These errors can be unintentional consequences of design bugs and neglected operating conditions or induced by intentional attackers. Recently, it has been shown that even more challenging threats exist where the attackers manipulate the hardware operations via malicious modifications of a hardware design before fabrication. Given the possibility of unintentional errors and maliciously modified hardware components and the difficulty of detecting all these issues, this project develops one last line of defense by monitoring fabricated hardware components during normal deployment and operation. This approach enables the detection of attacks or other conditions that violate the system's integrity and security. The project's novelties are the development of a rigorous approach for monitoring the operation of integrated circuits and the design of a software toolchain and hardware prototype that realizes the monitors. The project's impacts are advances in the reliability, safety and security of the hardware that forms the basis of computing systems. The project develops a novel monitor specification language, called FlowSL, for describing properties that are relevant for the integrity and security of a system. FlowSL goes beyond established approaches based on temporal logic and regular expressions in order to achieve a balance between expressiveness and being amenable to efficient execution on hardware. Principled heuristics and compilation algorithms are designed for the effective translation of monitor specifications into primitive hardware operations. The specification language is co-designed with a programmable hardware accelerator. The project designs highly optimized computational primitives in hardware, which are used for realizing individual operators of FlowSL, and a scalable and programmable pipeline architecture that enables the composition of several primitives to implement the monitors. A full-stack prototype is developed, which is evaluated on representative applications from the domains of hardware security and runtime verification of cyber-physical systems. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.