FuSe-TG: Electronic-Photonic Systems-on-Chip for Computation, Communication and Sensing

University Of California-Berkeley, Berkeley CA

Investigators

Abstract

The research vision is to create a breakthrough in the capability of future semiconductor technologies - to develop devices, circuits, systems, process, design flow and tools, and train students, in a novel platform for electronic-photonic systems-on-chip (EPSoCs) in advanced CMOS foundry processes, addressing a range of key applications in computing, communication and sensing. Semiconductor technology is entering a new age as the transistor scaling that has provided the past 50 years of progress slows down. Electronic-photonic (EP) integration offers a path to revolutionizing these capabilities via powerful new systems-on-chip (SoCs) for applications from optical input/output (I/O) today, through future radio frequency/mm-wave signal processing for 5G/6G wireless, light detection and ranging (lidar) imaging, and new paradigms for computing like artificial intelligence (AI) scale-out fabrics, photonics-interfaced superconducting electronics, and quantum computing. This path of innovation requires a convergent, interdisciplinary co-design approach intertwining the skills of photonics designers, electronic circuit/system designers, process engineers, and system/application experts. Researchers plan to utilize initial proof-of-concept developments to team with the domain and application experts and establish a base research and educational portfolio and a research team to shape the Center-scale Co-Design research effort. Monolithic electronics-photonics integration has been demonstrated by the members of the team - its use and advantage in classical optical interconnects, as well as the design of the first photon-pair source with integrated electronic sensing and control, molecular and ultrasound eletronic-photonic sensor systems-on-chip, a design of the mm-wave analog photonic link and a demonstration of the first cryo-photonic link. The goal in this work is to establish an effective co-design team with application domain experts to further develop the architectures and system-to-device modeling methodologies and co-design efforts along the three key research vectors in computation, communication and sensing, to establish a research and educational foundation for future Center-scale Co-Design research effort. Furthermore, these EPSoC concepts will be developed in a new, photonics-optimized high-volume electronic-photonic process (45nm SPCLO SOI CMOS) enabled by the team’s previous work. In the long-term, this work will create an EPSoCs platform that leverages state-of-the-art CMOS foundry technology. It will develop a framework (block libraries, tools, models and design methodologies) for low cost, rapid innovation and design of sophisticated EPSoCs. It will also democratize EPSoC technology making it accessible to a broader research, industrial and even educational community (e.g. making possible EPSoC chip design through open-source design tools and generator libraries). This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.