CCF: SHF: CORE: Small: Towards Systematic Quality Control of Physically Unclonable Functions (PUFs)

University Of Illinois At Chicago, Chicago IL

Investigators

Abstract

Physically Unclonable Functions (PUFs) are relatively new devices, often electronic, currently being designed and investigated for potential use as hardware security primitives for various security applications. Electronic PUFs work by exploiting some inherent randomness in the chip manufacturing process, which produces analog features with slight random variations that are combined to yield a digital function. This randomness, usually considered undesirable in traditional chip manufacturing processes, here is harnessed and, when coupled with an analog-to-digital process, realizes a "challenge-to-response" Boolean function. The hope is that each device's list of challenge-response-pairs (CRPs) is unique and hence may be used in security applications such as device identification, authentication, and on-demand cryptographic key generation. Strong PUFs promise a huge CRP space exponential in hardware size and hence able to generate, on demand, many and/or very long keys with minimal hardware throughout a device's lifespan. Despite the appeal of strong PUFs, few commercial realizations exist. To enable this, both 1) how to properly manufacture and test strong PUFs, and 2), once fabricated and tested, how to properly integrate such devices into security protocols need to be addressed. The latter is well studied; this award’s research will focus on the relatively unexplored former question. In this project, which brings together two faculty in complementary areas (statistics / information theory and electronic design automation / hardware security), the team will develop a systematic framework for the testing, diagnosing, repairing, and strengthening of strong PUFs. They will train undergraduate and Ph.D. students in testing and verification of hardware security primitives -- engineers with a deep understanding of this new area are indispensable for future trusted IC design and verification teams in the US. This research departs significantly from existing work on PUFs which has largely focused on either proposing new PUFs and evaluating their properties, or on security attacks / defenses of PUF-based protocols. Looking towards a future with ramped up domestic chip fabrication, the investigators focus on what would be needed to bring the promise of PUFs to fruition through: 1) developing new statistical, native fault models for PUF instances, PUF-production lines, and PUF-aging processes; 2) devising testing and diagnosing techniques able to quickly and accurately identify such faults. This could be fed back to electronic design automation tools to iteratively enhance PUF quality control. This differs markedly from existing testing techniques which test chips against a golden behavior. The investigators will also develop techniques to repair faulty, aging, or unreliable PUFs through challenge selection, which may be incorporated into PUF protocols. This line of work represents a careful and statistically motivated exploitation of the largely overlooked huge challenge space of strong PUFs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.