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Exploring the Limits of Scaling and 3D-integration for Edge-contacted Nanomaterial-based Transistors

$398,671FY2022ENGNSF

Duke University, Durham NC

Investigators

Abstract

Nontechnical: This NSF project aims to address longstanding questions related to the electrical interface between semiconducting nanomaterials and conducting metals. Nanomaterials show great promise for enabling a continuation of Moore’s law, which relates to the increase in computational capability using integrated circuits. By using nanomaterials for the semiconductor in transistors, these core computing devices can be scaled to smaller dimensions with increased performance compared to traditional semiconductors, such as silicon. Yet, there remain many questions about how electrical current flow is controlled between nanomaterials and contact metals. This project will bring transformative change to the field by using custom-designed device structures to study the behavior and control of electrical current at various metal-nanomaterial interfaces. Using what is known as an edge-contact geometry, both n-type and p-type nanomaterial-based transistors will be studied and ultimately demonstrated in a 3D integrated circuit. The intellectual merits of the project include addressing scientific questions related to how current is controlled at metal-nanomaterial interfaces at scaled dimensions. The new insights generated from these studies will advance the field of nanoelectronics through increased understanding of the scaling limits and evidence for a new approach to achieving 3D integration of devices. The broader impacts of the project include the advancement of devices for future integrated circuits and the engagement of students underrepresented in engineering. The advancements in this project can enable new integrated circuit designs for transistors to lower power consumption in energy-hungry applications such as data centers. Through this project, two graduate students from groups underrepresented in engineering will be supported, along with several new outreach initiatives to involve K-12 and undergraduates in the research effort. Technical: Nanomaterials offer many advantages for use in future transistor technologies. Yet, there remain scientific unknowns and obstacles to the fabrication and integration of nanomaterial-based transistors. This project seeks to address several longstanding questions related to metal-nanomaterial contact interfaces for 2D transition metal dichalcogenides (TMDs) and 1D carbon nanotubes (CNTs). Four distinct goals will be pursued, each relating to a specific aspect of metal-nanomaterial contacts. The first goal will be to address the question of whether contact gating in 2D transistors influences the contact length scaling behavior. Virtually all devices to date have included bottom-gate structures with the gate overlapping the source/drain contacts. This produces a gating effect on the semiconductor beneath the metal contacts and the influence of this effect has been hypothesized but never experimentally studied – such a study will be pursued with a large set of Molybdenum disulfide (MoS2) devices designed for characterization with and without an overlapping gate. The second goal will be to determine the impact of ambient air exposure during the fabrication of 1D edge contacts to 2D TMDs. Edge contacts are the most scalable because they only interface with the nanomaterial abruptly at the edge of the metal; however, there are very few reports of these contact structures and these contain conflicting claims regarding the influence of air exposure prior to metal contact deposition. A systematic and parametric study will be performed on four distinct edge-contact formation processes using 2D MoS2 and Tungsten diselenide (WSe2). The third goal will be to develop the first low-temperature (<400 C) edge-contact formation process for CNTs, which offer p-type devices that couple well with n-type MoS2 devices. Finally, the fourth goal will be to integrate the edge-contacted n-type MoS2 transistors with the edge-contacted p-type CNT transistors to demonstrate vertical monolithic integration that is back-end-of-line (BEOL) compatible; what’s more this demonstrated approach also cuts one masking layer out of the process by having the edge contacts formed in the same step as the contact vias. Overall, the results of pursuing these goals will be key scientific insights into metal-nanomaterial contacts applicable to a broad range of device applications. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

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Exploring the Limits of Scaling and 3D-integration for Edge-contacted Nanomaterial-based Transistors · GrantIndex