EAGER: High temperature superconducting thin film-based inductors and transformers for on-chip power management of 77K CMOS

University Of California-Los Angeles, Los Angeles CA

Investigators

Abstract

There is an increasing trend to operate microelectronics at low temperatures for both conventional electronics as well as superconducting electronics. At 77K liquid nitrogen temperatures, CMOS devices can operate at much higher speeds, and phenomena such as quantum computing can be exploited for more diverse applications. Cuprate based high temperature superconducting (HTS) materials are typically grown on ceria substrates. These films have high critical currents that make them quite useful at temperatures below ~80K. Unfortunately, they cannot be grown on silicon substrates since their temperatures of growth are too high for CMOS chips. This project aims to pattern Yttrium Barium and Copper Oxide (YBCO) available HTS materials into fine wires and magnetic components and transfer them via thermal compression bonding to silicon substrates and then separating them from their native substrates for eventual use in 77K CMOS based electronics. The objective is to design magnetic components such as on-chip transformers, inductors, and resonant coils for power delivery to conduct electrical signals with almost zero loss and very low energy. The project will prove the feasibility to pattern HTS materials into usable wires that can be applied to silicon chips. The project will educate students and the community on the processing and implementation of HTS materials for low temperature electronics. High temperature superconductors (HTS) have potential use in low temperature electronics especially for interconnects, magnetic components such as coils, transformers, and resonators. electronics. The project proposes to address two main challenges of patterning the HTS films into wires of micrometer dimensions; and to transfer these patterns to a silicon substrate for fabrication of inductors, coils, and transformers. HTS films grown with hetero-epitaxially ceria (Ce2O3) layers on sapphire substates will be patterned using RIE methods, since the process is widely used for scalability. Films will be separated from their native substrates either by laser-lift off or hydrogen implant-based exfoliation and will be thermal compression bonded (TCB) to the silicon substrate. The transferred patterned films will be characterized for degradation of superconducting, electrical, and structural properties. Smoothening techniques will be developed to address the intrinsically rough HTS surfaces. Magnetic coils and components fabricated will be electrically characterized at 77K for figures of merit and efficiency and will be compared with conventional copper interconnects. Successful completion will lay the foundation for a process to transfer of HTS wires-based interconnects to silicon chips, with extensive application in low temperature electronics. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.