CNS Core:Small:A HW/SW Codesign Framework For Dynamic Composition of Disaggregated Hardware Systems Securely

University Of California-Davis, Davis CA

Investigators

Abstract

Traditionally datacenters and high performance computing (HPC) facilities increase compute capacity by adding additional servers, which is increasingly becoming inefficient since emerging workloads exhibit very high peak to average memory requirements. Moreover, the fundamental building blocks of a modern data centers and HPC facilities (the processors) are becoming increasingly specialized with dedicated hardware for vector/tensor processing, deep learning, different memory pools such as DRAM, SRAM, and NVRAM, and special-purpose interconnect. Replicating such processors invariably results in hardware that is neither required nor useful all the time by all the applications. A disaggregated approach to computing system design can overcome these inefficiencies by selecting and composing the required hardware resources (e.g., accelerators, memory) to meet the requirements of a specific workflow or application. This project aims to make the design and implementation of such systems practical by addressing system security and performance. The intellectual merit of the proposed work lies in developing a new hardware software/codesign framework that is based on virtualized remote memory, object-level tracking for efficient data tiering and coherence, and flexible mechanisms to create and enforce hardware-based trusted execution environments. We will evaluate our solutions using a rigorous evaluation plan based on system-level modeling and simulation using the gem5 software infrastructure. Artificial intelligence and machine learning are expected to accelerate scientific discovery and play a very crucial role in addressing the grand challenges of the 21st century such as climate change, sustainability, and drug/vaccine discovery with broad societal impact. This project will enable training large scale machine learning models and perform large scale data analytics on disaggregated hardware systems which will allow them to be more performant and cost-effective. In addition, the modeling and simulation environment in gem5 broadly impacts computer architecture and computer systems researchers beyond this project. The models created in this project will be committed to the upstream gem5 project so that other researchers can use these models and build off of our designs. These contributions will impact the reproducibility and sustainability of this software infrastructure and advance computer architecture research in general. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.