CRII: SHF: Error Resilient Asynchronous Architecture for Ultra-Low Power Energy Harvesting IoT Applications

Florida Polytechnic University, Lakeland FL

Investigators

Abstract

This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2). As the demand for self-powered smart electronics and battery-less solutions increases, energy harvesting will be the power source of the future. Energy-harvesting devices operate on energy derived from ambient environmental sources or human activities. However, due to the limited energy density and irregular energy profile of different energy sources, such self-powered devices should be extremely energy-efficient and functional even under fluctuating supply voltages. Nowadays, most devices based on conventional synchronous (clocked) digital designs are extremely power-hungry, with the clock accounting for a significantly large portion of the consumed energy. Moreover, device miniaturization results in major design challenges, which makes clocked designs more susceptible to supply-voltage variations and unsuitable for devices operating on harvested energy. Asynchronous (clockless) designs can resolve the power inefficiencies associated with clocked designs, and have the potential to bring a whole class of applications into the domain serviceable by energy harvesting. With this vision, the primary objective of this project is to design error-resilient asynchronous circuits, which can create a venue to implement robust, unsupervised, maintenance-free, safe, sustainable, and low-power electronics for numerous energy harvesting-powered applications in different sectors, such as medical, space, defense, automobile, power industry, etc. The goal of this project is to develop a robust, reliable, and error-tolerant Quasi Delay Insensitive (QDI) asynchronous architecture for ultra-low power applications, which can perform energy-efficient computation and provide protection against radiation-induced transient errors in unsupervised scenarios. While numerous error-detection and -mitigation techniques exist for synchronous designs, there are very few for QDI asynchronous circuits. Also, the existing methods have major limitations, such as failure to ensure complete resilience, failure to halt error propagation in QDI pipelines, failure to circumvent duplication resulting in latency, energy, and area overhead, etc. This project aims to address these limitations by conducting research in two phases. The first phase will focus on 1) systematically analyzing the error response of QDI asynchronous circuits, and 2) developing a scalable and efficient formal framework to identify vulnerable components in both the data path and control path. The second phase will leverage the framework developed in the first phase to 1) critically analyze the vulnerable components and critical paths, 2) investigate possible architectural modifications for complete error-resilience, 3) ensure proper actions to prevent fault propagation through the QDI pipeline, and 4) perform cost/performance trade-off analysis of the newly developed architecture. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.