CAREER: Enabling Verifiable Computation with Hardware Acceleration

University Of California-Santa Cruz, Santa Cruz CA

Investigators

Abstract

This award is funded in part under the American Rescue Plan Act of 2021 (Public Law 117-2). As computation has become increasingly ubiquitous, so has the fraction of daily life directly impacted by it. Unfortunately, with declining trust in institutions, users find themselves in the perilous position of relying on computations they have little trust in. Fortunately, verifiable computation (VC), a rapidly emerging capability in computer science, provides a candidate solution. Instead of requiring users to blindly trust that their computations are correctly computed by others, users can verify that the correct computation was performed by inspecting a proof produced with the computation. There is a growing list of potential applications for VC including cloud offload, finance, untrusted chip fabrication, blockchain compression, and machine learning (ML). However, VC is currently impractical because generating the proofs is too computationally expensive. Hardware acceleration is a natural solution to VC's astronomical computational demands, but rising hardware-design costs complicate the development of specialized hardware. This project attacks both problems by investigating novel hardware architectures to accelerate VC and agile hardware-design techniques to reduce design costs. The acceleration provided will make many more VC applications practical. Enabling the widespread use of VC benefits society, as users will be able to individually verify the integrity of computations that affect them. The new design techniques will be shared in an approachable course whose materials will be open-sourced and well documented. In addition, the project integrates educational efforts such as helping underrepresented college students strengthen their problem-solving skills as well as broadening the pool of students pursuing graduate study. The immaturity of the VC research area complicates developing hardware acceleration in multiple ways, and this project is intended to solveee these challenges. First, VC is a diverse and rapidly moving field, which makes it unlikely that a single accelerator architecture will be able to support all approaches. Fortunately, many approaches reuse operations and computational patterns, so this project is creating a library of hardware generators that can serve as building blocks to construct the desired VC approaches. Second, since VC is so new, there is little architectural wisdom and nearly no prior work on hardware acceleration for VC. The flexibility and parameterizability of the generators enables expansive design space explorations to productively discover efficient architectures. Third, exploiting all of the opportunities for reuse requires non-trivial compositions of topologies, operators, and rich data types. The project is developing deep composition to raise the abstraction level of reuse without sacrificing efficiency. The innovative architectures developed to handle the novel VC workload will empower future VC application research. The open-source library of building blocks for VC hardware accelerators will help kickstart a new research area. Creating a new research area in addition to the new course and outreach activities, will help broaden and grow the hardware-design community. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.