Collaborative Research: FET: Medium: Neuroplane: Scalable Deep Learning through Gate-tunable MoS2 Crossbars

Northwestern University, Evanston IL

Investigators

Abstract

The increasing complexity of deep-learning systems has pushed conventional computing technologies to their limits. While the memristor is one of the prevailing technologies for deep-learning acceleration, it is only suited for classical learning layers where two operands, namely weights and inputs, are processed at a time. Meanwhile, to improve the computational efficiency of deep learning for emerging applications, a variety of non-traditional layers, requiring concurrent higher-order processing of many operands, are becoming popular. For example, hypernetworks improve their predictive robustness by simultaneously processing weights and inputs against the application context. Two-electrode memristor grids cannot natively support such operations of emerging layers. Addressing the unmet need, this research will develop Neuroplane -- a novel deep-learning accelerator of gated memtransistor crossbars. Exploiting crossbars' gate controllability, multiple operands can be processed within the same crossbar unit in Neuroplane. Many advanced inference architectures that can generalize beyond a typical passive crossbar will thus be possible. Overall, the ultra-low-power, higher-order processing of Neuroplane will harness high robustness and efficiency of emerging deep-learning layers within area/power-constrained devices such as mobile, sensor, and embedded systems. The investigators will develop fabrication methods for nanometer node gate-tunable dual-gated crossbars of MoS2 memtransistors. A self-aligned fabrication method with defect passivation and process variability compensation will be created. Exploiting the gate-tunability of MoS2 memtransistors, a new generation of crossbar platforms with many runtime control knobs will be developed, rendering the design a high elasticity and agile computing space. For example, computing methods will be created for the gated crossbars to utilize crossbar elements for product-sum digitization, thereby preventing the critical overheads in current crossbar technologies. Similarly, control-flow methods will be developed for gated crossbars to adapt their inference paths depending on the input characteristics by dynamically deactivating input/output neurons to conserve processing energy. A coherent collection of software and hardware-based correction techniques is proposed to minimize the impact of process variability. Unlike the current schemes, by following the train-once-deploy-anywhere tenet, the proposed crossbar correction methods can scale to millions of deployments without considerable overhead. An annual workshop will be conducted at local high schools with substantial ethnic and gender diversity to mentor underrepresented students. Undergraduate research projects will be sponsored using paid summer internships and university-level programs such as summer undergraduate fellowship. An inter-university senior-design mentoring program will be created for students among participating institutions. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.