SHF: Medium: PARIS: A New In-Sensor Computing Architecture for Intelligent 3-D Imaging Systems

University Of Rhode Island, Kingston RI

Investigators

Abstract

It is now a national research priority to design and develop novel computer hardware for artificial intelligence as well as smart sensing with capabilities for high-performance and energy-efficient computing. This project proposes a new architecture, PARIS (Phased Array Radar with In-Sensor Computing), that simultaneously senses and processes 3D images in real time. The new architecture mimics the human visual system, which not only detects and senses 3-D visual images but also performs first-stage image processing before the more complex processing in the visual cortex of brain. It is the first in-sensor computing architecture leveraging a phased-array radar system for an energy-efficient, high-performance, low-cost, and compact sensing/computing platform. By combining phased-array radar imaging and neuromorphic computing, PARIS opens up a new avenue for research in in-sensor computing and intelligent image processing. The project has transformative impact on a wide range of industries including medical instruments, autonomous vehicles, machine vision, robotic control, IoT devices, smartphones, and consumer electronics. Research activities of the project are involving female and minority students, strengthening the PIs’ current K-12 outreach activities, and enhancing grand-challenge courses for all majors at the university. It is well-known in artificial-intelligence systems that moving raw data from sensors to processing elements is very costly in terms of energy, performance, and hardware. The newly proposed architecture starts artificial neural-network computation concurrently while sensors are acquiring data, substantially reducing data movement between sensors and processing elements. Such simultaneous sensing and computation are made possible by several technology breakthroughs. 1) In-sensor dot-product computations with linearly tunable weights allowing in-sensor training and inference of artificial neural network; 2) a novel statistical signal acquisition technique, namely, Jitter-based Analog-to-Probability Conversion, allowing for direct use of digital pins of integrated circuits for high-bandwidth measurement with low-overhead; 3) a compact single-board system supporting very high radio frequency bandwidths and completely removing the radio frequency analog front-end required by conventional microwave imaging systems (e.g. analog-to-digital converter, filter, or amplifier) by leveraging the very short rising/falling edges of the digital waveforms used in today’s I/O interfaces. The theory and design of the in-sensor computing architecture is being established, and a 16-node prototype is being built. A thorough evaluation and comparison is being conducted to demonstrate its performance, energy efficiency, hardware cost, and potential applications to a wide range of industries. Research results are being published in professional conferences and journals and incorporated into undergraduate electrical/computer engineering curricula. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.