Collaborative Research: FET: Medium: Probabilistic Computing Through Integrated Nano-devices – A Device to Systems Approach

Purdue University, West Lafayette IN

Investigators

Abstract

The world has seen a steady increase in demand for computational power, with no end in sight. Search engines that allow users to find answers to pretty much all of their questions are expected to deliver results in less than a second, while understanding the customer with a high probability based on just a few words of input. This is not the type of computation that is precise and gives the “correct” answer; it instead provides solutions that are more associative, mimicking the human way of addressing problems. In fact, many problems in the real world are probabilistic in nature, and conventional computing schemes are not optimized for these tasks. In 1982 Nobel Prize winner Richard Feynman stated in recognition of this fact: “The way to simulate a probabilistic nature might still be by a computer which itself is probabilistic... So, it becomes what I’ll call a probabilistic computer, in which the output is not a unique function of the input.” To promote the progress of science, this proposal aims to explore, model and build hardware components and circuits that ultimately enable such a probabilistic computer, which will greatly benefit the society as a whole. Moreover, educational tools, new courses and training opportunities both for undergraduate and graduate students are being created that expose them to a device-to-systems research program on probabilistic computing in order to prepare them for the new era of electronics. The project adopts a Device-to-Systems approach that covers experiments from single devices and small circuits all the way up to simulations with thousands of devices. It addresses the question of how to implement probabilistic functionality in hardware from a variety of different angles. The key objective of this proposal is to take the next step in the development of probabilistic computing by experimental demonstrations of integrated probabilistic bits (p-bits) and p-circuits and quantifying advantages of scaled probabilistic computers through key figures-of-merits in system-level applications based on experimental input. This is being achieved by employing unstable magnets in a magnetic tunneling junction (MTJ) configuration as random number generators that become tunable by the use of field-effect transistors in a suitable circuit layout. Initial projections estimate that if integrated MTJs coupled with conventional transistors can be scaled up, one can expect to achieve orders of magnitude improvements compared to what is achievable in conventional semiconductor technology in key figures-of-merits, such as the number of statistically independent samples per second (also referred to as flips per second) that a probabilistic sampler can go through. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.