SaTC: CORE: Medium: Introducing DIVOT: A Novel Architecture for Runtime Anti-Probing/Tampering on I/O Buses

University Of Rhode Island, Kingston RI

Investigators

Abstract

This project introduces a new security technology that protects data confidentiality, data integrity, and correctness in computer systems. Specifically, the new technology is able to instantly detect malicious hardware attacks so that appropriate actions can be taken to prevent information from stolen and alteration when information is transmitted between components inside a computer system. The new technology can be realized using a simple digital hardware as part of a computer system. One of the objectives of this project is to design, develop, and implement the new hardware structure to be incorporated in future secure computers.  The direct outcome of this project is fundamental knowledge gained from theoretical study and experimental implementation of the new security architecture, referred to as DIVOT (Detecting Impedance Variation Of Transmission-lines).  DIVOT is a generic, scalable, and low-overhead security solution for any computer system. It is made possible by several new concepts including analog-to-probability conversion (APC) and probability density modulation (PDM). A runtime-accessible, CMOS-compatible, and I/O-integrated DIVOT hardware structure will be designed, implemented, and tested in this project. Integrating DIVOT with a variety of interconnecting transmission-lines will lead to a transformative secure and trustworthy architecture that substantially reduces attack surface. The broader impact of DIVOT architecture is significant.  It represents a universal countermeasure to fight against many physical probing/tampering threats and significantly enhances hardware security of various computing platforms ranging from servers to embedded computers in mobile devices and IoTs (Internet of things). Moreover, the outcomes of the project pave the way for many other future applications, including smart grid security, health care security, robotics security, etc. Many innovative architecture designs and security protocols will be generated that are likely to be published or transferred to the computer industry. Research results will be incorporated into our computer engineering curriculum. Experimental data will be stored in ASCII format, source codes will be in C language, FPGA implementation will be in Verilog or VHDL format, and technical papers/reports will be in PDF format. Besides technical publications, annual and final reports will be presented to NSF on research progress and discoveries. All the data will be retained for at least four years after conclusion of the project on PIs’ website: www.ele.uri.edu/~wei and www.ele.uri.edu/~qyang. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.