FoMR: IPC-MASTA: Boosting IPC with Microarchitectural Support for Tightly-Coupled Accelerators

University Of Wisconsin-Madison, Madison WI

Investigators

Abstract

Over fifty years of advances in high-performance microprocessors have enabled countless benefits to society, including unprecedented advances in many scientific disciplines and healthcare delivery, improvements in economic efficiency and productivity, new forms of entertainment, and the creation of entirely new industries and business models. However, both the computing industry and semiconductor technology are at a cross-roads, and new approaches are needed to sustain the historical trend of performance increases and overcome the barriers faced by conventional approaches to improving processor performance. A promising approach employed in recent designs has been to integrate function-specific hardware accelerators next to the processor, enabling efficient and high-performance offloading of common, coarse-grained, compute-intensive operations—such as decoding of video data—from the general-purpose CPU. This project will explore an emerging variant of this approach, where the accelerators are designed to perform frequent, fine-grained operations, are coupled tightly to the processor core, and are expected to be more flexible, broadly applicable, and easier to integrate into the software development model familiar to the vast majority of today’s programmers. This research is expected to lead to several practical artifacts along with scientific and conceptual advances that will enable designers of future microprocessors to more easily integrate such accelerators, as well as preparation and training of graduate students with potential for direct technology transfer through their future employment. This project seeks to conduct a detailed study of tightly-coupled accelerators (TCAs), uncovering the trade-offs and complexities of integrating them into modern processors. To date, little has been done to characterize and optimize the many design considerations that can have critical impact on overall processor performance and power consumption. The project will approach this problem in three phases. The initial phase will develop an analytical model for assessing the impact of integrating TCAs in high-performance CPUs. Next, a comprehensive study of the microarchitectural implications of TCAs will uncover key design challenges, opportunities, and novel solutions for integrating TCAs. The final phase will investigate reconfigurable TCAs, which are intended to achieve the seemingly contradictory goals of specialized acceleration as well as broad applicability. The project will investigate several avenues for general-purpose acceleration using our reconfigurable TCA architecture, showing that it is possible to reap the best of both worlds of specialization and generalization without dedicating significant hardware real estate nor design effort. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.