SHF: Small: Next-Generation Fully Integrated Power Management Circuits: Enabling Faster and More Efficient Computing and Communication in Smaller and Lower-Cost Mobile Electronics

Iowa State University, Ames IA

Investigators

Abstract

The semiconductor industry has increasing demands for faster and more efficient computing and communication with next-generation System-on-Chips (SoCs) and 5G new radios in thinner, smaller and lower-cost devices. The existing Power Management Integrated Circuits (PMICs), which are essential to supply power to different system components, cannot keep up with the needs of future applications, and become the most significant bottleneck in system development in respect of speed, form-factor and cost. This project aims to develop new designs of high-frequency voltage regulators fully integrated with all the components, including power inductors and capacitors, embedded in the integrated circuit package. The dynamic speed will be enhanced to enable optimal power-saving strategies for SoCs, which are essential to relax power and thermal constraints for higher performance. The enhanced speed will enable high-bandwidth envelop-tracking techniques, which will greatly reduce the power overhead in supplying radio-frequency power amplifiers in high-speed communication systems and improve the overall efficiency. The form factor and cost will be dramatically reduced. Besides, since power supply is fundamental in any electronic device, this project will potentially benefit a wide range of scientific, industrial, and medical applications. In addition, the research, education and outreach activities will also contribute to training the future science and engineering workforce and broadening participation in STEM areas. To accomplish the research goal, this project will develop fully integrated voltage regulators with multiple innovations, e.g., 1) new power inductors: develop near-free and high-quality power inductors with in-package parasitics to enable the freedom to expand the number of phases for faster speed, higher power capacity and better efficiency without increasing the form-factor and cost; 2) new topologies and design strategies: a) develop maximum efficiency-tracking strategies to determine the optimal number of phases at the design stage, as well as in operation; b) develop multi-level topologies for one-stage voltage conversion directly from the battery to the load; 3) new controller and circuits: a) push the small-signal bandwidth to the theoretical limit by developing a self-learning compensator; b) maximize the large-signal speed by developing a smart hybrid array and a burst-mode operation; c) design control and circuit techniques to switch the multi-phase and multi-level power stages with optimal efficiency; d) develop dynamic voltage stress management for stacking and multi-level topologies to support a wide voltage range with ensured reliability under high-frequency and high-current operations. The designs will be realized in silicon and measured with detailed performance characterizations. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.