SHF:Small: Machine Learning Approach for Fast Electromigration Analysis and Full-Chip Assessment

University Of California-Riverside, Riverside CA

Investigators

Abstract

Electromigration (EM) has become one of the most critical design issues and limiting factors for nanometer VLSI designs because of the shrinking size and increasing power density of the interconnects as technology scales down to sub 5nm. Due to its importance, many advances have been made recently in EM modeling and assessment techniques. However, fast and full-chip level EM analysis and validation still remain a challenging problem as completely modeling the EM failure process requires solving partial differential equations of hydrostatic stress in large interconnects. This will become even more difficult for full-chip level EM sign-off analysis. At the same time, machine learning, especially deep learning based on deep neural networks (DNN) such as convolutional neural networks (CNN), generative adversarial networks (GAN) and auto-encoders, is gaining much attention due to transformative successes in the many cognitive tasks. How to apply deep-learning techniques to learn and encode laws of physics and help to solve nonlinear partial differential equations, however, still remains in its infancy. The new EM optimization techniques will enhance the integrated-circuit (IC) design industry’s ability to improve VLSI long-term reliability amid continued aggressive transistor scaling and increasing power density. This research will also contribute significantly to the core knowledge and technologies of machine learning and data-driven based nonlinear dynamic-system modeling and advanced numerical approaches. This award will enable the investigator to hire more female and underrepresented minority students to further contribute to the diversity in America’s science and technology workforce. This project will explore novel and transformative EM modeling and full-chip EM-induced lifetime assessment techniques based on data-driven deep learning and advanced numerical methods. First, the research will investigate and design new deep-learning-based techniques for transient hydrostatic stress analysis for multi-segment interconnect trees. The project will explore DNN network structures such as CNN, GAN, autoencoders, and physics-informed neural networks for both void nucleation and post-voiding phases of EM failure processes in both circuit and full-chip levels. Second, the project will develop fast analytic and semi-analytic solutions for the stress-based partial differential equations for general multi-segment interconnects considering Joule-heating and thermal-migration effects. At the full-chip level, a coupled multi-physics analysis for fast EM sign-off check of on-chip power ground networks will be investigated. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.