SHF: Medium: Enabling Real-Time Federated Learning at the Edge: Algorithm and Circuit Co-Design

University Of California-Berkeley, Berkeley CA

Investigators

Abstract

Machine-learning applications are penetrating many new domains, and the increased concern for privacy is pushing training to the user devices, as opposed to being performed on large computers in the cloud. In the federated-learning paradigm, model training is performed on a large number of distributed devices with a user’s private local datasets, while the aggregate model is composed on the cloud. This approach poses a number of new challenges in both development and analysis of new algorithms and co-design of optimized hardware for efficient operation. For efficient deployment of federated learning, edge devices need to support many other aspects of interest for this program, among them on-device learning and incremental model updates with private data, often performed in real time. This project proposes to build an end-to-end, real-time federated-learning framework, ranging from algorithmic innovations, hardware-software co-design, and efficient hardware demonstrations in scaled technologies. Concurrently, the proposed education activities will enable the development of engineers and scientists whose expertise spans a broad range from algorithms to digital system implementation. The real-time machine federated-learning concept requires integration of theoretical algorithm aspects with their practical development. Theoretical aspects include the compression of model size, reduction in communication requirements and the assessment of performance. Practical aspects include efficient hardware for training and inference, randomized sketching with near-memory computation and hardware-aware neural network design. In particular, it aims to achieve: (1) A full demonstration of a scalable and energy-efficient real-time federated learning architecture suitable for deployment in various scenarios, (2) Experimental measurements via test chips and cloud-based FPGA simulation to validate the developed system models, (3) Release of the platform in the open source. The key products of this work integrate research and education and encompass scalable randomized sketching algorithms, energy- and cost-efficient machine-learning accelerators for on-device training, and fast-and-accurate hardware-modeling infrastructure for hardware-aware algorithm design. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.