SHF: Small: The Compiler-Architecture Solution to the Data Dependent, Circuit-Level Critical-Paths Variations

Northwestern University, Evanston IL

Investigators

Abstract

Computing performance translates to opportunities for innovations, which positively impact our society. Systems have experienced a steady performance improvement in the past. Unfortunately, recent developments in the semiconductor industry have made this progress hard to maintain, which has slowed down innovations in science and engineering. System performance depends on the capabilities of the compiler used and the underlying computer architecture. Usually, a compiler can control system activities at the instruction granularity while the underlying architecture hides finer-grained information. The compiler's inability to access fine-grained information, however, limits the overall performance obtainable in future systems. The project's novelty is a new compiler and computer architecture co-design where the latter enables the former to control activities at a much finer granularity compared to what has been explored before. This allows the underlying computer architecture to automatically boost the overall system performance as well as to save energy. The project's impact is to enable programmers to automatically make better use of the commodity processors. With processor performance increased, society will benefit from increased productivity and innovation in all areas involving computation. Recent developments in computer architecture have generated tremendous advances in single-chip core count as well as remarkable performance benefits brought by accelerators. However, Amdahl's Law reminds us that single-thread execution will always be the limiting factor for system performance -- a dire warning considering that the processor industry has fallen well short of the decades old sequential code performance growth trend. The team of researchers found that an important performance roadblock is in the sub-cycle domain where the circuit-level critical path latency depends on the data computed. This project designs a new compiler co-designed with the underlying architecture to access and control data-dependent, circuit-level critical path latencies. The impact of this design is the elimination of sub-cycle performance inefficiencies across the computation stack for commodity processors widely used in the whole computing spectrum, ranging from mobile to high performance computing. Code, data, and results emanating from the project will be maintained publicly at the website: http://users.cs.northwestern.edu/~simonec/SCDVCA.html This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.