IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design

University Of California-Riverside, Riverside CA

Investigators

Abstract

This IRES Track I project will support collaborative research to develop new algorithms and techniques for reliability-aware physical design and optimization of VLSI systems. U.S. students will be trained through collaborative research between two teams -- UCR's VLSI System and Computation Research Lab (VSCLAB) and Tsinghua University's Design Automation Lab. Each year five American students will participate in the IRES program. IRES students will spend 10 weeks (one academic quarter) at UCR and 10 weeks at Tsinghua University, China. Specific IRES collaborative research, education and culture activities are planned to expose U.S. undergraduate or graduate students to the global engineering education and research environment through US-China academic collaboration. The collaborative educational and research activities will provide unique training, mentoring, networking and intellectual development opportunities for students at UCR, which is a growing and Minority Serving Institution. This project thus provides a unique opportunity to contribute to diversity in the U.S. technical workforce. Such international engagement will benefit the students' entire careers and make them more competitive and competent in their careers as scientists and engineers. Furthermore, building long-term connections with top-tier engineering schools like Tsinghua University will help U.S. scientists and engineers maintain competitiveness in the long term. Finally, the joint research will strengthen existing computer engineering research and education programs, and broaden the collaborative research work at UCR. The IRES collaborative project will produce important research advances through joint development of efficient algorithms and design methodologies to address the grand challenges of reliability-aware physical design and optimization of VLSI systems. The researchers will work on the most severe and challenging aspects of verification and design problems of silicon CMOS based integrated systems in current and coming 10nm/7nm nodes: modeling, analysis of long-term interconnect reliability effects such as electromigration (EM), time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and reliability-aware physical design and optimization. The mutual interests and complementary knowledge, and established trust between the two research teams is critical for the success of the student training, mentoring and the proposed joint research project. The education and research activities of this joint project consist of following activities: student training, mentoring and intellectual development via pre-trip preparation and on-site visits; new courses and seminar development for proposed research topics; joint research projects and student supervision and publications; promoting and nurturing diverse cohorts of U.S. students; evaluation for continuous improvement of the program. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.