I-Corps Teams: Seeking Commercialization Potentials of a New Interconnect based Nanoscale Computing Technology for Future Digital Integrated Circuits

University Of Missouri-Kansas City, Columbia MO

Investigators

Abstract

The broader impact/commercial potential of this I-Corps project can be significant as it can provide pathways for commercialization of a breakthrough research for continuous miniaturization of computer chips. For the digital electronics in everyday use, smaller and better chips imply lesser cost, higher performance, and more features. As traditional way of IC scaling reaches unsurmountable barriers at sub-10nm technology nodes, the proposed technology provides new directions for scaling through innovations in several layers from fundamental physical components, computing model, to circuits and integration. In addition, the technology promises denser, faster and more power efficient computing with unique capabilities for fault-tolerant and secure hardware through inherent physical capabilities and design choices. The technology, coupled with Intellectual Property (IP) development strategy based fabless commercialization approach is proposed for market penetration and growth at a fast turn-around time. The product will be beneficial for a wide range of customers from microprocessor producers to consumer electronics manufacturers and be particularly attractive for defense entities. This I-corps teams project will allow customer discovery, business model generation and evaluation of commercialization potentials for successful SBIR/STTR proposals, and can ultimately lead to the transition of lab research to product. It will have a lasting impact on the participants. This I-Corps project seeks commercialization potential of a novel computing technology that relies on deterministic interference between adjacent nanoscale interconnects (Crosstalk) for logic computing. The proposed approach departs from current device switching dependent computing paradigm and relaxes difficult device scaling requirements. The scalability in Crosstalk fabric is determined primarily by circuit scheme, integration and the ability to pattern smaller metal nano-lines and deposit dielectrics in between them, which can be done by utilizing existing EDA and manufacturing methods. The proposed computing approach is functionally complete, and provides huge opportunities for logic reduction; by having more than 2 inputs couple to a single output and by varying their respective coupling capacitances, a logic implementation (e.g., Carry logic for Addition) that would typically require more than 15 transistors in CMOS, can be done by just 5 transistors. The benchmarking of a 4-bit adder showed over 5x density benefits vs. CMOS at 16nm. Another distinct feature of Crosstalk technology is the run-time reconfigurability that allows different functionalities to be embedded in the same circuit, which can be transformative for fault tolerance (i.e., if a portion of CPU is damaged, the functioning portion can be configured to do both tasks), and cybersecurity. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.