FoMR: Collaborative Research: Single-Thread Multi-Accelerator Execution to Close the Dennard Scaling Gap

University Of Wisconsin-Madison, Madison WI

Investigators

Abstract

With ever-slowing scaling trends in microprocessor technologies, traditional techniques of improving processor performance are no longer viable, and achieving higher performance requires a dramatically different approach. This project develops a multicore chip microarchitecture using specialized accelerators and code-injection techniques without needing to modify user-level software, compilers and operating systems. The impact of this research is to help steer microprocessor design in novel ways that can help sustain performance improvements, especially for datacenter and big-data computing. This project builds on a recent promising technique involves offloading program phases onto specialized processors (accelerators) which are tuned to execute programs with specific characteristics (i.e., parallelism, control dependence, memory behavior) at extremely high efficiency. There are two main challenges which motivate the major thrusts of this work. The first is the question of how to design a practical system for managing the execution of heterogeneous accelerators and dynamic translation. The second is how to design a set of accelerators which provide integer factors of improvement over general purpose processors' performance and energy efficiency. This work addresses the first challenge by designing a disaggregated translation subsystem, including region detection hardware at each core, a set of disaggregated compiler cores and a translation cache, and a hardware/software layer which dynamically re-maps logical threads to physical cores based on dynamic code properties and load balancing. To design a set of balanced accelerators, this work is analyzing programs to identify key program behaviors, and developing targeted accelerators for each. Finally, this includes the design of synthesis-time resource allocation algorithms which will co-optimize the choice of cache interface, general core attributes, and accelerator execution model. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.