SHF: Small: Soft-FET: Phase Transition Material Based Soft Switching Field Effect Transistor for Energy Efficient CMOS

University Of Texas At Austin, Austin TX

Investigators

Abstract

With the rapid advances in computing systems spanning from billions of IoT (Internet of Things) devices to high performance exa-scale supercomputers, energy efficient design is an absolute must. In a modern System-on-a chip (SoC) design, supply voltage scaling is the primary driver to reduce the energy consumption. Voltage droops caused by the peak switching current as well sudden changes in current activity of various logic blocks requires larger voltage guard-bands, thereby degrading the system level energy efficiency. Thus, there is a critical need to develop circuit topologies to reduce the peak switching currents as well as sudden current fluctuations to reduce the voltage droops and to realize a compact and energy-efficient power delivery network. Principles underlying the research in this project can be readily transferred to existing SoC designs benefiting the integrated chip design industry, and ultimately the consumer society. The students engaged in this research will be trained in device fabrication, integrated circuit, test-chip design, and heterogeneous system integration issues, thus contributing to the much needed workforce development in chip design industry. This research envisions a novel soft-switching transistor architecture named as Soft-FET for realizing energy-efficient CMOS circuits. The targeted efficient operations can be realized by utilizing abrupt phase change behavior in transition metal oxides. The project will fabricate and demonstrate Vanadium Dioxide (VO2) based Soft-FET integrated circuit prototype by heterogeneous integration with baseline CMOS technology. Various Soft-FET architecture circuit blocks such as digital logic, SRAM bitcells/arrays, I/O buffers, power gates, and power converters will be investigated to realize energy efficient CMOS designs. If successful, this research can improve the energy efficiency of integrated circuits by lowering the voltage droop guard bands. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.