CAREER:Enabling Scalable, Modular, and Efficient Architecture Specialization Fabrics

University Of California-Los Angeles, Los Angeles CA

Investigators

Abstract

Past exponential improvements to computer processor capabilities are now being threatened by a long-term slowdown of the progress in physical device technologies. An alternate approach is to specialize processor design for a small set of tasks, sacrificing generality for improved performance and energy-efficiency. However, if hardware specialization is relied on too much, the pace of innovation for new and fast-moving applications will be stifled. Hence, new techniques are required to balance the fundamental trade-offs between the efficiency of specialized processors with the usefulness of general processors. A promising way forward is the development of specialization fabrics, where the software interface and hardware implementation are co-designed to enable efficient execution of programs with broad application characteristics. This CAREER award develops the principles behind building such fabrics, addressing their two main challenges. The first is scalability: how to support vast amounts of computational units without mitigating the benefits of specialization. The second is modularity: how to enable simple tailoring of the fabric to a particular design setting (e.g. for a datacenter machine, phone, or wearable) through composable hardware. The broad potential of this work is to enable principled specialized hardware which can continue to bring exponential performance and energy improvements, both through dissemination of discovered principles and through open source releases of hardware and software. For industry, the developed frameworks can enable hardware companies to leverage zero-design-effort hardware tailored for their use cases. For academia, these can lower the cost of entry of hardware/software co-design research, and enable researchers to make cross-domain innovations more easily. This framework is being integrated into courses to teach the fundamental interactions between hardware and software. Overall, the broad goal of this work is to create a programmable accelerator fabric, scalable to high throughput, and whose features can be modularly composed - ultimately enabling accelerator-like performance and energy efficiency across many domains. Intellectually, it furthers the unification of two disparate fields of computer architecture, the study of on-chip memory systems and the study of architectural specialization. The project develops the principles of scalable and modular specialization fabrics through two thrusts. The first explores how to leverage high-level ISA constructs to rethink the design of the cache hierarchy and on-chip communication network for specialization fabrics, which are typically constrained by communication bandwidth or access/storage energy. The key innovation is to expose to the memory system a set of higher level abstractions describing coarse-grain patterns of memory access. Leveraging this information can reduce the inefficiencies of communication and tag/redundant cache access, but requires a significant overhaul to existing protocols to maintain simple memory semantics. The second thrust develops a framework for composing modular architecture features to enable trivial hardware customization for vastly different application domains. The key innovation is the development of high-level ISA features which have a direct correspondence to composable hardware structures. This thrust develops a template design and instruction-set description for composing ISA-exposed microarchitecture features, explores a set of ISA features for regular and irregular workloads, and develops a compiler to hide ISA complexity. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.