CRII: SHF: A Memory-Centric Hardware Accelerator for Large Scale Data Clustering

University Of Utah, Salt Lake City UT

Investigators

Abstract

Clustering is a crucial tool for analyzing data in virtually every scientific and engineering discipline. The U.S. National Academy of Sciences (NAS) has recently announced "the seven giants of statistical data analysis" in which data clustering plays a central role. This report also emphasizes that more scalable solutions are required to enable time and space clustering for the future large scale data analyses. As a result, hardware and software innovations that can significantly improve energy-efficiency and performance of the data clustering techniques are necessary to make the future large scale data analysis practical. To this goal, the proposed research demonstrates a radically different vision of solving data clustering problems in the future, where large-scale clustering problems are mapped onto a memory-centric, non-Von Neumann computation substrate and solved in situ within the data arrays, with orders of magnitude greater performance and energy efficiency than contemporary computer systems. The proposed project will leverage recent developments in resistive random access memory (RRAM) and algorithmic approaches for reformulating clustering problems within massively parallel frameworks, such as bit serial rank order filters, to build an extremely low power and fast memory substrate for future clustering applications. At the software level, novel algorithms will be developed to map different types of heterogeneous data clustering problems (including numerical and non-numerical data points) from scientific and engineering domains onto the proposed memristive accelerator. Programming models, software modules, and application libraries for hardware-software co-design, dynamic resource management, and memory allocation will be developed to give the user control of the data clustering process at runtime. At the hardware level, we will investigate techniques for optimizing power and performance of the memory modules constructed from novel resistive cells and interconnection networks. Architecture and software innovations will be disseminated to the broader research community through published papers, as well as tutorials on the emerging in situ computing platforms and software-hardware interfaces in non-Von Neumann computer systems. The educational component of this project will involve integrating the cell structure, the interconnection networks, the hierarchical software interface, and the control policies into the syllabus of an advanced computer architecture course.