CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology

The University Of Central Florida Board Of Trustees, Orlando FL

Investigators

Abstract

Many very large scale integration circuits deployed in the Internet of Things and in various high performance applications are required to support the use of high performance and low performance modes in order to minimize power consumption. Such circuits are synchronized by a clock signal that is distributed using a clock network. The clock network is required to reliably deliver the clock signal even while the circuit is under the influence of manufacturing and environmental variations. This research project will result in a clock network synthesis tool that is capable of reliably synchronizing components on circuits that operate in multiple modes. Moreover, a course on computer-aided design and research opportunities will be provided to students at the University of Central Florida. The robustness and power consumption of a clock network is mainly dependent on the topology of the network. Existing clock networks have a topology in the form of a tree, near-tree, or non-tree. In this project, a synthesis tool that is capable of constructing clock networks with a mode reconfigurable topology will be developed. In high performance modes, the required robustness to variations is provided by reconfiguring the clock network into a near-tree topology. In low-performance modes, the power consumption is reduced by reconfiguring the clock network into a tree topology. Moreover, the proposed clock network structure has no short circuit current, regardless of whether the topology is reconfigured to be in the form of a tree or near-tree. No short circuit current is introduced in the proposed structure because there is only a single gate driving each net of interconnects. In particular, the project involves developing an entire-clock-network-at-the-same-time methodology. Techniques of reconfiguring the topology and improving the robustness of delivering both the rising and falling edge of the clock signal will be explored. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.