SHF: Small: Distributed Timing Analysis and Beyond

University Of Illinois At Urbana-Champaign, Urbana IL

Investigators

Abstract

In order to design next generations of complex microelectronic systems, major innovations in the design of EDA (Electronic Design Automation) software are needed. Timing analysis is a core EDA technology. It is the task of analyzing the timing of electrical signals propagating through various parts of the chip, thus allowing designers to determine if a design meets performance requirement. Given the ever-increasing chip design complexity, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design process. A typical approach to mitigate this issue is to break down a chip design into several partitions and run timing analysis in parallel using the multiple cores in a single computer. For today's billion-scale designs, generating timing reports can consume up to 400 GB memory. The proposed research will advance knowledge in EDA by addressing this need. It will also add new knowledge to other fields such as general distributed computing and network optimization since ultimately we will need to solve large-scale optimization problems in distributed environment. The broader impacts of this project include microchip design technology advancement and the education of next generation engineers. Microchips are at the heart of modern information and communication systems. The proposed research improves chip design technology that will benefit the society at large. New research results will be passed on to undergraduate and graduate students through dissertation research, course projects, homework, and classroom teaching. As the design complexity continues to grow larger, building a high-end computer is neither cost-effective nor scalable. Therefore, recent trends are driving the requirement for distributed timing analysis (DTA) in EDA tools. However, DTA has by far received little research attention and remains a critical problem. A successful distributed timer means not only a faster path to design completion but also the chance of breaking cumbersome design hierarchies, which has the potential to tremendously improve the overall quality of design. Distributed timing is also one of the major hurdles to overcome for EDA to be cloud-friendly, which is believed to deliver the next leap of design productivity and unleash new opportunities. This research proposal proposes to build an efficient, scalable, robust and secure distributed timing analysis system.