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I-Corps: Customizable and scalable high-performance microprocessor

$50,000FY2017TIPNSF

University Of Wisconsin-Madison, Madison WI

Investigators

Abstract

The broader impact/commercial potential of this I-Corps project is to enable superior performance and energy efficiency for cost-sensitive embedded processors. As computing devices have become ubiquitous and permeated every aspect of life, the need for greater performance has also followed. However, traditional design techniques to enable high performance microprocessors incur resource costs and typically suffer from poor energy efficiency. These overheads come at a considerable cost as most embedded designs are energy constrained and highly cost sensitive. The byproduct of these competing design constraints has been stagnating progress due to the ineffectiveness of traditional techniques. Through the use of this project's novel processor microarchitecture, commercial designs should observe approximately 30% greater energy efficiency and superior performance without incurring resource overhead. Applications such as networking and storage domains are initial candidates for adopting the design. This I-Corps project focuses on the creation of an energy-efficient microcontroller through the use of a novel processor microarchitecture. At the time most fundamental microprocessor techniques were developed, power was not a problem and transistors were scarce. To satisfy these constraints, designs focused on maximizing utilization of the few execution resources present. As transistors became more plentiful and performance of greater importance, designs utilized these additional transistors to enable complex organizational and scheduling techniques to maximize the operation of the scarce execution resources. This project's architecture reverses this trend by allocating additional transistors to execution resources and greatly simplifying organizational and scheduling overheads. Initial research suggests that considerable energy and area efficiency gains are possible while maintaining a high level of performance in comparison to current commercial designs. Additionally, the novel structure of this microprocessor enables many optimizations that are impractical in conventional designs due to their complex organization and scheduling.

View original record on NSF Award Search →