SBIR Phase I: Energy and Space Efficient Power Management Integrated Circuits for Mobile Devices

Silicon6, Llc, Leander TX

Investigators

Abstract

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to bring to market a novel power chip architecture for battery-operated electronics, such as smartphones, wearable electronics, electric vehicles, blade servers, cloud-infrastructure hardware, telecom devices, tablets, routers, LED lightning, etc. There are four critical requirements of the power management integrated circuits (PMIC) when used in mobile devices: (1) high energy efficiency for a longer battery run-time between charges; (2) small solution size by freeing up extremely limited space for new functionalities; (3) fast response speed for wide variety of uses; and (4) simplified circuit design for shortening new products' time-to-market. Currently, no solutions are capable of simultaneously meeting the above four requirements. It has become necessary to consider a new topology that could help enabling more efficient Internet of Things designs. It is therefore an object of this proposal to develop novel power chips where the above four requirements can be easily met. Consequently, for any direct current powered mobile devices, as long as they are consuming large power, struggling with limited spaces, and requiring efficient cooling effects, the proposed solution aims to achieve the optimal performance. Unlike the present power management integrated chip (PMIC) solutions that have to lose one or more features for a certain improvement, the proposed intellectual merits achieve all of the important features in one single architecture without losing anything. The new PMIC architecture has been preliminarily verified using computer modeling simulation based on ideal circuit models. The objective of this project is to develop new power management chips for use in smartphones and to achieve optimal testing results when verified with 180 nanometer CMOS processes. The R&D scope includes intellectual property core block circuits design, reusable sub-module testing, and mixed signal top-level simulations where the combination of all blocks and modules will be thoroughly represented, within which a circuit that will be etched onto the wafer in Phase II must function correctly. This work?s goal is to demonstrate that the proposed PMIC architecture is a valid solution to fundamentally address the major pain points in the mobile device market.