Context-Sensitive Decoding: Exploiting Translated ISAs for Security, Safety, Energy, and Performance

University Of California-San Diego, La Jolla CA

Investigators

Abstract

Context-Sensitive Decoding allows a processor with a translated instruction set architecture (such as x86, and often ARM) to decode a given instruction into a different set of micro-ops, depending on conditions set, for example, by the operating system. This allows the system to transparently add features (for security, performance, energy efficiency, debugging, etc.) to executing code with no changes to the code or access to the original sources. It could be used to add security features to unknown code with significantly reduced cost, and thus move closer to the point where such security can be always turned on. Context-sensitive decoding can be used to add a level of specialization to general-purpose processors (an industry dominated by US-based companies) that better enables them to compete with domain-specific specialized solutions, with no significant changes to current pipelines. Many modern processors translate the programmer-visible instruction set architecture (ISA) to a separate, simpler internal ISA. This research makes that traditionally static translation dynamic, where instructions can be decoded/translated differently based on context. For example, we can seamlessly transition from a performant (traditional) translation to a secure translation that now includes data address randomization by setting a single flag in the processor. In addition to security, other applications abound in areas such as programming languages (e.g., on demand type safety, range checking, etc.), software engineering (full-performance debug mode), profiling and performance programming (performance counters of much greater variety than supported natively in hardware, seamlessly enabled or disabled), etc.