SI2-SSE: 3DSIM: A Unified Framework for 3D CPU Co-Simulation

University Of Maryland, College Park, College Park MD

Investigators

Abstract

Performance enhancements and increased energy efficiency that could be obtained by reducing the dimensions of transistors is becoming difficult. Thus, Moore's law no longer holds true for conventional approaches to chip design. Three-dimensional (3D) integration of chip components has emerged as an innovative packaging alternative to conventional approaches where multiple layers of silicon are stacked and interconnected using directly through the silicon layers (this technique is known as "Through Silicon Via" or TSV). Using TSVs and 3D packaging enables significant benefits to the performance, functionality and energy efficiency of future CPUs. However, 3D integration results in new types of interaction patterns between computing cores and between core and memory components. In addition, the close proximity between cores and memory causes their physical attributes, such as their temperature, noise of power delivery, and reliability to become uniquely interdependent. If innovations in 3D integration are to continue, substantial investment in frameworks that can simulate and evaluate 3D computer architectures are necessary. This project seeks to develop such a simulation framework and make it available to the computer architecture design community. The objective of this project is to develop a full system simulator for 3D CPUs while accounting for the architectural and physical interactions between the cores and memory components thereby allowing the co-simulation of power, performance and reliability characteristics. The framework supports a wide array of 3D CPU configurations including intricate specifications of cores, core counts, network on chip protocols, on-chip/off-chip caches, main memory and off-chip secondary storage (built using diverse set of devices including SRAM, DRAM, non volatile devices). The project is a substantial addition to the repertoire of 3D integrated circuit design and simulation frameworks and shall play a vital role in future innovations in 3D CPU architectures.