NeTS: CSR: Medium: Collaborative research:Wireless Datacenter-on-Chip (WiDoC): A New Paradigm for Big Data Computing

Washington State University, Pullman WA

Investigators

Abstract

This project focuses on a new paradigm for Big Data computing, namely a Datacenter-on-a-Chip (DoC) consisting of thousands of cores that can run compute- and data-intensive applications, orders of magnitude more efficiently compared to existing platforms. Indeed, nowadays data centers and high performance computing clusters are dominated by power, thermal, and area constraints; they occupy large spaces and necessitate sophisticated cooling mechanisms to sustain the required performance levels. In contrast, this project relies on emerging many-core processors that can run Big Data applications while provisioning the system resources for the necessary power/performance/thermal trade-offs. Consequently, various big data applications like social computing, life sciences, networking, or entertainment, can benefit immensely from this new design paradigm that aims at achieving server-scale performance from hand-held devices. The proposed work introduces a new direction in networked system design enabled by the emerging wireless on-chip interconnect paradigm. Indeed, achieving DoC level of massive integration requires significant innovation at multiple levels of abstraction, ranging from the design of the on-chip network and associated physical layer, all the way to mapping and runtime management of various applications. To this end, the research goals include: - Design of a small-world wireless network architecture as a communication backbone for manycore-enabled wireless DoC (WiDoC) - Design methods at physical layer for highly-integrated 3D wireless DoC suitable for low latency data communication - Evaluation of various latency-power-thermal (LPT) trade-offs for the proposed WiDoC platform with relevant big data applications. While most of the prior work considers 2D many-core platforms where communication happens through wired links, this proposal redefines the very foundations of on-chip communication via 3D small-world network architecture with sub-THZ wireless links in the planar layers and inductive coupling-based wireless interfaces in the vertical direction; this allows for full flexibility and reconfiguration and makes such platforms suitable for processing big data applications at unprecedented levels of energy efficiency. The proposed research is unique as it brings together highly novel and interdisciplinary concepts from network-on-chip (NoC), wireless, and complex networks, communication circuits, and optimization techniques aimed at single chip solutions for achieving data center-scale performance. The educational contribution of this work will help establishing an interdisciplinary research-based curriculum for high performance many-core system design meant to increase the number of students attracted to this area of engineering.