Heterogeneous III-V CMOS on Si via Direct Growth

University Of Southern California, Los Angeles CA

Investigators

Abstract

III-V semiconductors hold performance records for a vast majority of electronic and photonic device categories, from transistor speed to photovoltaic conversion efficiency. However, the inability to cost-effectively integrate high material quality III-V's with substrates amenable to volume manufacturing, such as Si wafers has limited the adoption of III-V materials to applications that can absorb the high costs of III-V growth. This limitation arises from the fundamental lattice mismatch between the III-V semiconductors of interest and the underlying Si substrate. While a variety of approaches have been developed to address this challenge, they often rely on complex buffer layers and face challenges when tightly integrating different materials on the same layer. Here, a recently developed growth technique that enables growth of crystalline III-V's on non-lattice matched substrates will be utilized to demonstrate heterogeneous III-V CMOS logic circuits on Si. Importantly, the technique used here will potentially dramatically reduce the cost of III-V integration. In addition to the specific demonstration of logic circuits, the integration of III-Vs with Si can potentially impact a wide ranges of areas such as photonics, sensing, and photovoltaics. To advance STEM education and diversity as part of this project, a joint effort with a local high school is being undertaken to build integrated physics and math lesson plans that aid students in seeing how complex math concepts are utilized to build models for the physical world. The specific goal of this research is to demonstrate indium phosphide, indium arsenide, and gallium antimonide based III-V CMOS logic circuits directly grown on Si substrates. Critically, the growth studied here involves precipitation of the desired III-V crystal out of a liquid phase metal solvent, in contrast to the vapor-solid growth phases used for traditional MOCVD growth. This work will be carried out by first performing detailed structural and electronic material characterization of III-Vs grown on Si, using techniques such as x-ray diffraction, transmission electron microscopy, electron backscatter diffraction, Hall measurements, photoluminescence yield, and time resolved photoluminescence measurements. Utilizing these techniques, we will establish how growth parameters affect the formation of defects in the III-Vs, and how those defects impact the optoelectronic characteristics of the materials. Finally, III-V n-channel and p-channel FinFETs and circuits will be fabricated and characterized focusing on both individual devices and materials co-integration issues. Furthermore, the materials and processes developed here will be of importance for a wide range of fields including electronics, photonics, imaging, and photovoltaics.