SHF: Small: Efficient In-Memory Computing Architecture Based on RRAM Crossbar Arrays

Regents Of The University Of Michigan - Ann Arbor, Ann Arbor MI

Investigators

Abstract

Conventional digital computers, with separate processor and memory, face increasing challenges in today?s ?big data? era as the constant movement of data between the processor and the memory causes significant delay and energy consumption. This problem, termed the ?von Neumann bottleneck?, affects performance for both complex tasks such as image and video processing as well as embedded applications such as distributed sensor networks where high speed and low power are critical. This project aims to develop a new computer architecture based on emerging resistive random access memory (RRAM) crossbar arrays, where the memory and logic functions exist at the same physical locations and computation is achieved in the physical memory by directly reading out stored outputs for a given operation. By leveraging the unique properties of emerging devices with a new computation architecture, this project will profoundly advance the frontier of nanoscale device and computer architecture research, and enable high-speed and low-power computation for applications ranging from servers to Internet of Things (IoTs). This program will have significant impact on the research community and the semiconductor industry, while providing interdisciplinary training of graduate and undergraduate students, and draw broad participation of students of different levels and backgrounds in collaborative research and education. This approach takes full advantage of the high-storage density, non-volatility, and random-access capabilities of RRAM arrays. RRAM devices operate based on the resistance change when the device is subjected to a programming or reset pulse. Consequently, the resistance not only stores information but also directly regulates information (i.e. current) flow in the circuit, thus implementing both memory and logic functions simultaneously. Previous studies on RRAM-based circuits focus on soft computing tasks where the environment and the tasks are complex but inaccuracies and approximations are tolerated. This project aims to develop a computing system that can perform accurate arithmetic operations efficiently using RRAM crossbar arrays. The system will be optimized for throughput and energy, and experimentally demonstrated using fabricated high-density RRAM arrays, along with the development of a toolset for design automation.