SHF: Small: Hardware-Software Co-Designed Coherence: A Complete Coherence Solution for Performance-, Energy-, and Complexity-Efficiency

University Of Illinois At Urbana-Champaign, Urbana IL

Investigators

Abstract

As the benefits from transistor scaling slow down, future performance increases in computing systems will increasingly rely on architectural advances. Today processors use parallelism and increasing amounts of specialization to provide this performance growth. An efficient memory hierarchy is key to achieving the full potential of both of these techniques. The coherence protocol and memory consistency model are at the heart of the complexity-, performance-, and energy-efficiency of the memory hierarchy. Unfortunately, across a variety of systems, coherence protocols and consistency models continue to struggle to obtain an appropriate balance between complexity, performance, and energy consumption. Recently, there has been work on hybrid hardware-software co-designed protocols, exemplified by the DeNovo protocol, which takes a different approach, combining the best of pure hardware and pure software protocols. The key insight is that if software is disciplined, then it is possible to design more efficient hardware. Multiple versions of the DeNovo system have successively relaxed the software restrictions. Introducing such a new technology in classrooms to both graduate and undergraduate students will better prepare them for future memory trend and challenges. Disseminating the results of this research via publications, seminars, tutorials etc. will bring new technology awareness to the community and create more synergy among academia and industry.   Prior work has established the potential for DeNovo as a general-purpose system with significant advantages over the state-of-the-art. However, this work of necessity has been limited to simple workloads. Consideration of DeNovo as a viable system for widespread industrial adoption requires demonstrating an integrated system that can run complex workloads (e.g., operating systems) and legacy binaries. This project addresses the remaining research issues to achieve this goal. Although this work is driven by considerations for hybrid hardware-software coherence protocols, the intellectual contributions extend beyond those protocols as well; e.g., integrated support for efficient, coherent data accesses using a variety of disciplines ranging from completely unstructured to highly structured, statically analyzable accesses; a systematic exploration of relaxed atomics, a widely accepted difficulty in current memory consistency models; and understanding concurrent data structures and system code in a coherence neutral way.