SHF:SMALL:Pushing the Limits of Transparent Specialization

University Of Wisconsin-Madison, Madison WI

Investigators

Abstract

For many years, microprocessors took advantage of how Moore's Law (smaller successive generations of transistors) and the fact that they consumed less power to build better performing chips. Due to fundamental limitations it is no longer possible to cost-effectively make smaller transistors or significantly reduce their power consumption. This research project develops future microprocessors that are organized differently and more effectively using limited transistors to provide better chips. The main idea this research project explores is a way to tailor certain parts of a chip to certain tasks, thereby making each component very small and power-efficient. A program's execution moves from one such component to another, each being tuned for that phase of the program. The curriculum enhancements will provide students significant experience in designing hardware. This research will help steer microprocessor designs in novel ways to sustain performance improvements and help sustain information technology leadership. The specific approach taken by this research is a unique and novel form of specialization called: behavior specialized acceleration (BSA). This is a paradigm that exploits program behaviors and their inter-relationship to hardware microarchitecture. It is workload domain agnostic. Specializing for program behaviors is advantageous both because fewer accelerators can target a large variety of codes, and because these behaviors are typically analyzable by a compiler, meaning their use can be transparent from programmers. In particular the research will develop a chip organization that includes an ExoCore fabric and an Endocore fabric. The ExoCore fabric is a processor core organization that uses behavior specialization to transparently improve the execution of general-purpose workloads. The Endocore fabric employs different behavior specializations and attempts to support computationally-intensive domains using a single hardware architecture and well-defined software interfaces. This research develops mechanisms, an FPGA prototype of a family of ExoCore and EndoCore designs, their accompanying compiler, and detailed performance evaluation.