CRII: SHF: Investigation of Effective On-chip Network Designs for GPUs

Oregon State University, Corvallis OR

Investigators

Abstract

Graphics Processing Units (GPUs) have been proliferating at an extraordinary speed in the past decade. Continuing innovations in related technologies allow today?s GPUs to play critical roles in numerous disciplines and sectors as well as many emerging fields that might not otherwise be possible. Examples include processing ambient video inputs in automobiles for enhanced safety and intelligent driving; powering graphics-based medical processing applications in mobile devices for ubiquitous biometric monitoring and personalized healthcare; supporting virtual reality headsets for transformative and immersive new experiences in education, training, and entertainment; and providing energy-efficient parallel computing in HPC systems and data-centers to facilitate a myriad of scientific, economic, and social computing applications. Such promising developments are enabled by the massively parallel computing capacity of GPU architectures, which can integrate thousands of processing cores on a single chip. To continue meeting growing performance expectations, on-chip interconnect architectures must be developed to provide fast and efficient communications among the vast number of processing cores in GPUs. This research investigates cross-cutting approaches and techniques to improve the effectiveness of on-chip networks (or NoCs) in GPU systems. The objective is to fully explore the challenges and develop framework useful for GPU NoC designs that will meet the performance, energy, and resource efficiency targets of current and future GPU systems. Among some of the specific aspects investigated are the bottlenecks of NoCs in the GPU context, alternative methods of enabling scale-up, sensitivity of NoCs to various types of GPU applications, and the impact of NoCs on GPU system-level trade-offs. This research also investigates opportunities in coordinated design among NoC components as well as co-optimizations between NoCs and other GPU subsystems. The objective is to enable on-chip networks to operate more consistently and efficiently for the overall benefit of GPU systems by factoring in multiple components and key application characteristics. Beyond its specific technical contributions to fundamental advancements in computing, this research has broader potential impact to society through its activities on research education and outreach that aim to broaden participation for people from diverse background, including groups underrepresented in engineering at various education levels.