CAREER: Trading Communication and Storage for Computation to Enhance Energy Efficiency

University Of Minnesota-Twin Cities, Minneapolis MN

Investigators

Abstract

Looking forward, a fundamental challenge in computer systems is the Power Wall, where, due to imbalances in technology scaling, not all the compute engines that find place on chip can be powered on at the same time. The Power Wall is transforming all levels of the system stack, including the parallel architecture landscape. Communication power, as induced by data movement and the orchestration thereof, along with storage power, dominates computation power. As the degree of concurrency increases, communication power becomes even more prominent due to more frequent data transfers. At the same time, emerging memory technologies are not mature enough to keep up with the corresponding capacity, bandwidth, and performance requirements within a tight power budget. An amnesic processor, can minimize, if not eliminate, the power and performance overhead associated with data storage, retrieval, and communication, thus, operate more energy efficiently. The limited storage of the amnesic machine represents the short-term memory, which lacks long-term memory by construction.  When compared to its classic counterparts, an amnesic machine can facilitate more compute engines to occupy the area once devoted to (long-term) memory, which can further be harnessed for recomputation. Recomputation can transparently convert workloads to become more compute intensive such that they can make a better use of classic architectures optimized for performance, as opposed to energy efficiency. This project intends to unlock the energy efficiency premise of amnesic machines. To this end, the PI proposes to explore compiler and microarchitecture support to decide when to replace remote loads with re-computation. The research has three major thrusts: (i) at compiler time, integer linear programming based optimization will be performed to generate a probabilistic energy-minimal re-computation schedule; (ii) runtime controller will be designed to decide when to re-compute based on the information the compiler provides; and (iii) memory hierarchy will also be explored to maximize energy efficiency. Interaction with emerging technologies and reliability issues will also be considered. The integrated education and outreach plan includes workshop organization, undergraduate curriculum, and Eureka! program for K-12 girls .