CCSS: Emulating Mixed-Signal VLSI Systems

Stanford University, Stanford CA

Investigators

Abstract

Proposal 1509126 PI: Mark Horowitz Institution: Stanford University Title: Emulating Mixed-Signal VLSI Systems Project Goals: To validate combined analog and digital VLSI chips, we create functional models of the analog components which run on digital logic emulators. Nontechnical Technology scaling created an environment of ubiquitous computing: we now have singing cards, and computer controlled cars, and soon all these devices will be connected to the net. The Internet of Things is one of the most promising areas in computing research today. Yet there is a fundamental problem that must be addressed if we are going to fully realize the promise of a fully connected world: how to validate the complex mixed-signal integrated circuits that are the foundation of this revolution. Since these chips tightly couple analog and digital blocks, we need to validate the entire analog/digital system together. Attacking the mixed-signal validation issue is a key challenge that must be addressed to enable this new future, and it is the topic of this research. Technical: Recent work has started to address this issue, by creating models of the analog blocks that can be run in a digital validation environment. This research extends this prior work in two way. First it will address some of the limitations of the current analog modeling work to both make it more general (handle more types of situations that occur in real circuits), and codify the procedure for creating these models. This first extension will make it much easier to use the current modeling technique. Unfortunately chip systems are so complex today that software based simulation is often too slow for system validation. As a result most companies rely on hardware emulation platforms for validation. Thus our second goal is to further extend our analog function modeling by creating a system that can map these functional models onto a platform currently used for hardware emulation. These emulation platforms either consist of field programmable logic arrays (FPGAs) or custom built emulation chips. We will explore two approaches to analog functional mapping directly mapping all analog blocks to FPGA logic, and building an analog model interpreter and choose the most cost effective approach. Since the direct mapped approach can maintain a fixed ratio between the rates of the clocks used for the analog and digital blocks, it might make sense to build simple oversampled analog models. Here the challenge is in mapping the required computation to the FPGA. Most analog functions can be mapped to digital blocks, implemented with lookup tables (LUTs) and filter/DSP blocks. In the interpreter approach, we will explore building an analog model evaluation engine that will emulate a model when its inputs change. If the analog signals change more slowly than the main FPGA clock, we might have many cycles for each model evaluation, making this a more efficient approach. In addition, it is possible that we can build many fewer model evaluation engines than analog functional models.