SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies

University Of Arizona, Tucson AZ

Investigators

Abstract

Power dissipation has become a fundamental barrier to scaling computing performance across all platforms from handheld, embedded systems, to laptops, to servers to data centers. Technology scaling down to the sub-nanometer regime has aided the growth in transistors per chip that has made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. The computing capabilities of these multi-core architectures can be unleashed only if the underlying Network-on-Chip (NoC) connecting the cores can provide the required bandwidth within the power budget of the chip. However, the design of power-efficient, low-latency and high-bandwidth NoCs using traditional metallic interconnects that can scale to 1000 cores and beyond, is proving to be a significant challenge of enormous proportions. Research has shown that emerging technologies such as photonics and wireless have the potential to alleviate the critical bandwidth, power, and latency challenges of future NoCs. However, hybrid NoC designs taking advantages of both photonics and wireless technologies have not been explored. This research proposes to lay the groundwork for completely re-thinking the NoC design and proposes to explore heterogeneity of emerging interconnect technology for designing performance scalable, and power-efficient NoCs. The overall objective is to combine multiple technologies to achieve our challenging goals of (1) scalability to 1000 cores, (2) power efficiency of at least a 50% power reduction as compared to the state-of-the-art metallic interconnects, and (3) high bandwidth and low latency across a wide variety of applications. First, at the architecture level, optics will be deployed for short-range (< 100 cores) to improve local communication and wireless for long-range communication in order to scale the number of cores to 1000 by providing sufficient global bandwidth. Second, at the circuit level, hybrid transceiver architectures will be explored to integrate novel ultra-low power wireless circuits based on SiGe/BiCMOS technology with optical waveguides and ring-resonators to provide the large bandwidth desired for kilo-core designs. Furthermore, wireless communication requirements will be addressed by designing mm-wave/THz frequency broadband and directional antennas based on advanced 3D printing technology. This proposal describes a transformative and viable approach combining technology, architecture, algorithms and applications research for designing scalable and energy-efficient NoCs. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies.