CCF: Medium: Collaborative Research: SHF: Cascode: Supporting and Leveraging Voltage Stacking in Future Microprocessors

University Of Rochester, Rochester NY

Investigators

Abstract

Power dissipation is increasingly becoming the central issue in almost all computing and communication systems from mobile devices to warehouse-scale systems. This project investigates a technology that can shave off at least a few percent of chip energy of all chips by targeting one particular aspect of power consumption that has not received as much attention as others: power delivery. In addition to the team of investigators, the project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the nation?s workforce in information technologies. Today's chips operate at low voltages (about 1V) to reduce power consumption. However, delivering the power at low voltage is problematic. For instance, it results in more delivery loss (in the real world, electricity is transported at voltages thousands of times higher than that of the usage voltage). This project will be investigating a solution called the Cascode power delivery system, which stacks multiple planes of circuit to naturally increase the effective usage (and therefore delivery) voltage. This design is not only likely to bypass some fundamental problems with other means of increasing power delivery voltage (such as using on-chip voltage converters), but also to creates new architectural opportunities such as improved communication circuits with higher voltages and better capabilities to compensate variations in the fabrication process.